參數(shù)資料
型號: AD1981BLJSTZ-REEL
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: AC 97 SoundMAX Codec
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: LEAD FREE, MS-026BBC, LQFP-48
文件頁數(shù): 6/32頁
文件大?。?/td> 326K
代理商: AD1981BLJSTZ-REEL
AD1981BL
Parameter
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to High Z Delay
Propagation Delay
RESET Rise Time
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
Rev. A | Page 6 of 32
Symbol
t
SYNC_PERIOD
t
SETUP
t
HOLD
t
RISECLK
t
FALLCLK
t
RISESYNC
t
FALLSYNC
t
RISEDIN
t
FALLDIN
t
RISEDOUT
t
FALLDOUT
t
S2_PDOWN
t
SETUP2RST
t
OFF
Min
5
5
2
2
2
2
2
2
2
2
0
15
Typ
20.8
2.5
4
4
4
4
4
4
4
4
Max
6
6
6
6
6
6
6
6
1.0
25
15
50
15
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
1
Guaranteed but not tested.
2
Output jitter is directly dependent on crystal input jitter.
3
Maximum jitter specification is for noncrystal operation only. Crystal operation maximum is much lower.
0
RESET
BIT_CLK
SDATA_IN
t
RST_LOW
t
RST2CLK
t
TRI2ACTV
t
TRI2ACTV
Figure 2. Cold Reset Timing (Codec is Supplying the BIT_CLK Signal)
0
SYNC
BIT_CLK
t
SYNC_HIGH
t
SYNC2CLK
Figure 3. Warm Reset Timing
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