參數(shù)資料
型號: AD1981BLJSTZ-REEL
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: AC 97 SoundMAX Codec
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: LEAD FREE, MS-026BBC, LQFP-48
文件頁數(shù): 5/32頁
文件大?。?/td> 326K
代理商: AD1981BLJSTZ-REEL
AD1981BL
Parameter
Low Level Output Voltage (V
OL
), I
OL
= 2 mA
Input Leakage Current
Output Leakage Current
POWER SUPPLY
Power Supply Range (AV
DD
and DV
DD
)
Power Dissipation
Analog Supply Current—3.3 V (AV
DD
)
Digital Supply Current—3.3 V (DV
DD
)
Power Supply Rejection (100 mV p-p Signal at 1 kHz)
1
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
CLOCK SPECIFICATIONS
1
Input Clock Frequency
Recommended Clock Duty Cycle
Rev. A | Page 5 of 32
Min
10
10
3.0
Typ
2.87
39
48
40
Max
0.1 × DV
DD
+10
+10
3.47
Unit
V
μA
μA
V
mW
mA
mA
dB
40
24.576
50
MHz
%
60
1
Guaranteed but not tested.
2
Measurements reflect main ADC.
POWER-DOWN STATES
Values presented with V
REFOUT
not loaded.
Table 3.
Parameter
Fully Active
ADC
DAC
ADC + DAC
Mixer
ADC + Mixer
DAC + Mixer
ADC + DAC + Mixer
Standby
Headphone Standby
Set Bits
No Bits Value
PR0
PR1
PR1, PR0
PR2
PR2, PR0
PR2, PR1
PR2, PR1, PR0
PR5, PR4, PR3, PR2, PR1, PR0
PR6
DV
DD
Typ
47.76
40.1
32.8
13.2
47.7
40
32.77
13.9
0
47.7
AV
DD
Typ
38.9
34.39
26.3
20.55
19.39
14.86
6.39
1.15
0
32
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
TIMING PARAMETERS
Guaranteed over operating temperature range.
Table 4.
Parameter
RESET Active Low Pulse Width
RESET Inactive to BIT_CLK Start-Up Delay
SYNC Active High Pulse Width
SYNC Low Pulse Width
SYNC Inactive to BIT_CLK Start-Up Delay
BIT_CLK Frequency
BIT_CLK Frequency Accuracy
BIT_CLK Period
BIT_CLK Output Jitter
1, ,
BIT_CLK High Pulse Width
BIT_CLK Low Pulse Width
SYNC Frequency
Symbol
t
RST_LOW
t
RST2CLK
t
SYNC_HIGH
t
SYNC_LOW
t
SYNC2CLK
t
CLK_PERIOD
t
CLK_HIGH
t
CLK_LOW
Min
162.8
162.8
32.56
32.56
Typ
1.0
1.3
19.5
12.288
81.4
750
42
38
48.0
Max
±1
2000
48.84
Unit
ms
ns
μs
μs
ns
MHz
ppm
ns
ps
ns
ns
kHz
2 3
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