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參數(shù)資料
| 型號： | AD1974YSTZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC 4CH ADC W/PLL 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 429mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個差分，單極 |
AD1974
Data Sheet
Rev. D | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AV
DD
48
LF
47
ADC2RN
46
ADC2RP
45
ADC2L
N
44
ADC2L
P
43
ADC1RN
42
ADC1RP
41
ADC1L
N
40
ADC1L
P
39
CM
38
AV
DD
37
DV
DD
13
AUX
DAT
A2
14
AUX
DAT
A1
15
NC
16
AUX
BCL
K
17
AUX
L
RCL
K
18
AS
DAT
A2
19
AS
DAT
A1
20
ABCL
K
21
AL
RCL
K
22
CI
N
23
CO
UT
24
AGND
1
MCLKI/XI
2
MCLKO/XO
3
AGND
4
AVDD
5
NC
6
NC
7
NC
NC = NO CONNECT
8
NC
9
PD/RST 10
NC 11
DGND 12
AGND
36
FILTR
35
AGND
34
AVDD
33
AGND
32
NC
31
NC
30
NC
29
NC
28
CLATCH
27
CCLK
26
DGND
25
AD1974
TOP VIEW
(Not to Scale)
SINGLE-ENDED
OUTPUT
06614-
020
Figure 2. AD1974 Single-Ended Output, 48-Lead LQFP Pin Configuration
Table 10. Pin Function Description
Pin No.
Type1
Mnemonic
Description
1, 4, 32, 34, 36
I
AGND
Analog Ground.
2
I
MCLKI/XI
Master Clock Input/Crystal Oscillator Input.
3
O
MCLKO/XO
Master Clock Output/Crystal Oscillator Output.
5, 33, 37, 48
I
AVDD
Analog Power Supply. Connect to analog 3.3 V supply.
6 to 9, 11, 16, 28 to 31
NC
No Connect.
10
I
PD/RST
Power-Down/Reset (Active Low).
12, 25
I
DGND
Digital Ground.
13
I
DVDD
Digital Power Supply. Connect to digital 3.3 V supply.
14
I/O
AUXDATA2
Auxiliary Data Input 2 (From External ADC 2).
15
I/O
AUXDATA1
Auxiliary Data Input 1 (From External ADC 1).
17
I/O
AUXBCLK
Auxiliary Bit Clock.
18
I/O
AUXLRCLK
Auxiliary Left-Right Framing Clock.
19
I/O
ASDATA2
ADC Serial Data Output 2 (ADC 2 Left and ADC 2 Right)/ADC TDM Data Input.
20
O
ASDATA1
ADC Serial Data Output 1 (ADC 1 Left and ADC 1 Right)/ADC TDM Data Output.
21
I/O
ABCLK
Serial Bit Clock for ADCs.
22
I/O
ALRCLK
Left-Right Framing Clock for ADCs.
23
I
CIN
Control Data Input (SPI).
24
I/O
COUT
Control Data Output (SPI).
26
I
CCLK
Control Clock Input (SPI).
27
I
CLATCH
Latch Input for Control Data (SPI).
35
O
FILTR
Voltage Reference Filter Capacitor Connection. Bypass with 10 F||100 nF to AGND.
38
O
CM
Common-Mode Reference Filter Capacitor Connection. Bypass with 47 F||100 nF to AGND.
39
I
ADC1LP
ADC1 Left Positive Input.
40
I
ADC1LN
ADC1 Left Negative Input.
41
I
ADC1RP
ADC1 Right Positive Input.
42
I
ADC1RN
ADC1 Right Negative Input.
43
I
ADC2LP
ADC2 Left Positive Input.
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