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參數(shù)資料
| 型號： | AD1892JRRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Integrated Digital Receiver/Rate Converter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 231K |
| 代理商： | AD1892JRRL |
AD1892
–8–
REV. 0
SERIAL DIGITAL AUDIO TRANSMISSION STANDARDS
The AD1892 can receive S/PDIF (Sony/Philips Digital Interface
Format), AES/EBU (Audio Engineering Society/European
Broadcasting Union, also known as AES3-1992), IEC-958
(International Electrotechnical Commission) and CP-340 (EIAJ
[Electronic Industry Association of Japan] CP-1201) serial
streams. S/PDIF is a consumer audio standard, and AES/EBU
is a professional audio standard; IEC-958 and CP-340 have
both consumer and professional definitions. This data sheet is
not intended to fully define or to provide a tutorial for these
standards; please contact these international standards setting
bodies for the full specifications.
All of these digital audio serial communication schemes encode
audio data and audio control information using the biphase-
mark method. This encoding method minimizes the dc content
of the transmitted signal and allows the receiver to decode clock
information from the transmitted signal. As can be seen from
Figure 1, ones in the original data end up with midcell transi-
tions in the biphase-mark encoded data, while zeros in the origi-
nal data do not. Note that the biphase-mark encoded data
always has a transition between bit boundaries.
0
1
1
1
0
0
0
1
0
0
1
0
1
0
1
1
1
1
BIPHASE-MARK
DATA
DATA
CLOCK
(2 TIMES BIT RATE)
Figure 1. Biphase-Mark Encoding
Digital audio communication schemes use “preambles” to dis-
tinguish between channels (called “subframes”) and between
longer term control information blocks (called “frames”). Pre-
ambles are particular biphase-mark patterns, which contain
encoding violations that allow the receiver to uniquely recognize
them. These patterns, and their relationship to frames and
subframes, are shown in Figures 2 and 3.
BIPHASE PATTERNS
11100010 OR 00011101
11100100 OR 00011011
11101000 OR 00010111
CHANNEL
X
Y
Z
LEFT
RIGHT
LEFT AND C.S. BLOCK START
Figure 2. Biphase-Mark Encoded Preambles
PREAMBLES
X LEFT CH Y RIGHT CH Z LEFT CH Y RIGHT CH X LEFT CH Y RIGHT CH X
SUB-
FRAME
FRAME 191
FRAME 0
FRAME 1
START OF CHANNEL STATUS BLOCK
SUB-
FRAME
Figure 3. Preambles, Frames and Subframes
The biphase-mark encoding violations are shown in Figure 4.
Note that all three preambles include encoding violations. Or-
dinarily, the biphase-mark encoding method results in a polarity
transition between bit boundaries.
PREAMBLE X
PREAMBLE Y
PREAMBLE Z
1
1
0
1
1
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
0
Figure 4. Preambles
As noted above, these serial digital audio communication
schemes are organized using a frame and subframe construction.
There are two subframes per frame (ordinarily the left and right
channel). Each subframe includes the appropriate four bit
preamble, four bits of “auxiliary” (aux) data, 20 bits of audio
data (LSB first), a “validity” (V) bit, a “user” (U) data bit, a
Channel Status (C) bit and an even parity (P) bit. The Channel
Status bits and the user bits accumulate over many frames to
convey control information. The Channel Status bits accumu-
late over a 192 frame period (called a Channel Status block).
The user bits accumulate over 1176 frames when the inter-
connect is implementing the so-called “subcode” scheme
(EIAJ CP-2401). The organization of the Channel Status
block, frames and subframes is shown in Figure 5.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD1892JRZ | 制造商:Analog Devices 功能描述:Receiver/Rate Converter 28-Pin SOIC W |
| AD1893 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter |
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| AD1893JNZ | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W |
| AD1893JST | 制造商:Analog Devices 功能描述:Sample Rate Converter 44-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:LOW COST ASRC 44-PIN TQFP - Tape and Reel 制造商:Analog Devices 功能描述:IC ASR CONVERTER 16 BIT |
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