參數(shù)資料
型號(hào)： AD1892JRRL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： Integrated Digital Receiver/Rate Converter
中文描述： SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝： SOIC-28
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 231K
代理商： AD1892JRRL
AD1892
–14–
REV. 0
CONTROL/STATUS REGISTER ARCHITECTURE
The AD1892 includes two byte-wide control registers, two
byte-wide status registers, four Channel Status registers and ten
RESERVED
RESERVED
RESERVED
RESERVED
CHANNEL STATUS
LEFT/RIGHT
USER/CHANNEL
STATUS BIT
PORESET
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
00 0000
00 0001
CONTROL REGISTER 0
CONTROL REGISTER 1
CONTROL BUFFER – 2 BYTES
RESERVED
DITHER
MUTE
SMONO
DOUTPUT
DOUTPUT
DOUTPUT
FRBCLK
BASRC
Figure 20. Control Registers
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CHANNEL STATUS
LEFT/RIGHT
USER/CHANNEL
STATUS BIT
POWER-DOWN/
RESET
CONTROL REGISTER 0
00 0000
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
1 = POWER DOWN (STOP CLOCKS) AND RESET
0 = NORMAL OPERATION (DEFAULT)
1 = OUTPUT CHANNEL STATUS BIT ON U/CBIT PIN
0 = OUTPUT USER BIT ON U/CBIT PIN (DEFAULT)
1 = CHANNEL STATUS INFORMATION FROM LEFT CHANNEL OUTPUT
ON CA THROUGH CE AND CON/
PRO
0 = CHANNEL STATUS INFORMATION FROM RIGHT CHANNEL OUTPUT
ON CA THROUGH CE AND CON/
PRO
(DEFAULT)
MUTE
SMONO
DOUTPUT
FRBCLK
ASRC BYPASS
00 = I2S COMPATIBLE (DEFAULT)
10 = RIGHT JUSTIFIED
11 = RESERVED
1 = 16-BIT
1 = 32 TIMES FS
0 = 64 TIMES FS (DEFAULT)
CONTROL REGISTER 1
1 = MONO ((L+ R)/2) ON BOTH LEFT AND RIGHT CHANNELS
0 = NORMAL STEREO OPERATION (DEFAULT)
1 = MUTE DIGITAL AUDIO OUTPUT
00 0001
D7
D6
D5
D4
D3
D2
D1
D0
OUTPUT
DATA FORMAT
DITHER
1 = RATE CONVERSION BYPASS
0 = NO RATE CONVERSION BYPASS (DEFAULT)
1 = PROPERLY DITHER OUTPUT DATA TO SELECTED WIDTH
0 = NO DITHER (DEFAULT)
OUTPUT
DATA FORMAT
Figure 21. Control Register Bit Definitions
NO PHASE
LOCK
CH. STATUS
CRC ERROR
INTERRUPT
(MIRRORS PIN)
ERROR
(MIRRORS PIN)
CHANNEL
STATUS CHANGE
ERROR
PARITY
CODING
VIOLATION
STDAT
Q-CHANNEL
Q-CHANNEL
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESET TO 0
MODE
MODE
GSTATUS
NUMBER
RESERVED
ADDRESS
TRACK
INDEX
MINUTE
SECOND
FRAME
ZERO
ABSOLUTE
MINUTE
SECOND
ABSOLUTE
FRAME (Q97)
CACODE
CCODE
CACODE
CACODE
CCODE
CACODE
PRE-EMPHASIS
PRE-EMPHASIS
PRE-EMPHASIS
CCOPY/
NAUDIO/
PRO/CON
CATEGORY
CODE
NUMBER
NUMBER
NUMBER
SOURCE
SOURCE
SOURCE
SOURCE
NUMBER
SAMPLE
FREQUENCY
SAMPLE
FREQUENCY
SAMPLE
FREQUENCY
SAMPLE
FREQUENCY
CLOCK
ACCURACY
CLOCK
ACCURACY
RESERVED
ADDRESS
ADDRESS
ADDRESS
CONTROL
CONTROL
CONTROL
CO(Q2)
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
NUMBER
INDEX
MINUTE
SECOND
FRAME
ZERO
INDEX
MINUTE
SECOND
FRAME
ZERO
INDEX
MINUTE
SECOND
FRAME
ZERO
INDEX
MINUTE
SECOND
FRAME
ZERO
INDEX
MINUTE
SECOND
FRAME
ZERO
INDEX
MINUTE
SECOND
FRAME
ZERO
INDEX
MINUTE
SECOND
FRAME
ZERO
ABSOLUTE
MINUTE
SECOND
ABSOLUTE
FRAME
ABSOLUTE
MINUTE
SECOND
ABSOLUTE
FRAME
ABSOLUTE
MINUTE
SECOND
ABSOLUTE
FRAME
ABSOLUTE
MINUTE
SECOND
ABSOLUTE
FRAME
ABSOLUTE
MINUTE
SECOND
ABSOLUTE
FRAME
ABSOLUTE
MINUTE
SECOND
ABSOLUTE
FRAME
AMINUTE
ASECOND
AFRAME
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
00 0000
00 0001
00 0010
00 0011
00 0100
00 0101
00 0110
00 0111
00 1000
00 1001
00 1010
00 1011
00 1100
00 1101
00 1110
00 1111
STATUS REGISTER 0
CHANNEL STATUS BYTE 0
Q-CHANNEL SUBCODE BYTE 0
STATUS REGISTER 1
CHANNEL STATUS BYTE 1
CHANNEL STATUS BYTE 2
CHANNEL STATUS BYTE 3
Q-CHANNEL SUBCODE BYTE 1
Q-CHANNEL SUBCODE BYTE 2
Q-CHANNEL SUBCODE BYTE 3
Q-CHANNEL SUBCODE BYTE 4
Q-CHANNEL SUBCODE BYTE 5
Q-CHANNEL SUBCODE BYTE 6
Q-CHANNEL SUBCODE BYTE 7
Q-CHANNEL SUBCODE BYTE 8
Q-CHANNEL SUBCODE BYTE 9
STATUS BUFFER – 16 BYTES
Figure 22. Status Registers—Consumer Mode
Q-Channel subcode registers. The bit map of the Control Reg-
isters are shown below in Figures 20 through 23.
The bit map of the status registers in consumer mode are shown
below in Figure 22.
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