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參數(shù)資料
| 型號： | AD1892JR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Integrated Digital Receiver/Rate Converter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 231K |
| 代理商： | AD1892JR |
AD1892
–4–
REV. 0
AD1892 PIN LIST
Biphase-Mark Serial Input
Pin Name
SOIC
I/O
Description
RXP
RXN
13
14
I
I
Positive differential biphase-mark serial digital audio receiver input. 20 mV hysteresis.
Negative differential biphase-mark serial digital audio receiver input. 20 mV hysteresis.
Serial Output Interface
Pin Name
SOIC
I/O
Description
SDATA
24
O
Serial output, MSB first, containing two channels of 16 to 20 bits (default) of twos-complement
data per channel, depending on control register settings. The data can be configured in I
2
S-justified
(default), left-justified, and right-justified orientations, depending on control register settings. See
Figure 36 for timing.
Bit clock output for output data. Frequency is either 32
×
F
S
(packed mode) or 64
×
F
S
(default),
depending on control register settings. See Figure 36 for timing.
LEFT/
RIGHT
clock output for output data. Runs continuously and is a synchronous divide-down
from MCLK (MCLK/512). See Figure 36 for timing.
The SYNC input allows multiple AD1892s in a system to be phase and group delay synchronized to
the same LEFT/
RIGHT
clock. The SYNC signal resets internal AD1892 counters such that 512 MCLK
cycles after the falling edge of SYNC, the AD1892 data will be valid, and the AD1892 L
R
CLK signal
will change state. It is recommended that the SYNC input be used only when the AD1892 is in the
64
×
F
SOUT
BCLK mode (default configuration). GND when not in use.
BCLK
26
O
L
R
CLK
25
O
SYNC
23
I
Decoded Channel Status Outputs
Pin Name
SOIC
CA
21
I/O
O
Description
In consumer or professional mode, CA is the inverse of Channel Status Bit 1, Byte 0 (
C1
, audio/
nonaudio). CA = 0 indicates nonaudio, CA = 1 indicates audio. CA = 0 can be used to indicate
Dolby AC-3 encoded data.
In consumer mode, CB is the inverse of Channel Status Bit 2, Byte 0 (
C2
, copy/copyright). CB = 0
indicates copy permitted/copyright not asserted; CB = 1 indicates copy inhibited/copyright asserted.
In professional mode, CB is defined as EM0, the least significant bit of the two bits that encodes the
emphasis status of the audio material.
CB
20
O
(continued from Page 1)
PRODUCT OVERVIEW (Continued)
In addition to the Q-channel subcode and Channel Status buff-
ers, the AD1892 includes two 8-bit control registers and two 8-
bit status registers. The output data interface may be configured
in left-justified, I
2
S-justified and right-justified modes. The
AD1892 includes hardware power-down/reset and mute control
inputs, and power-down/reset and mute may also be invoked
through write to bits in the control registers. The AD1892
operates from a master clock that must be synchronous with the
output sample rate at 512
×
F
S
. Cyclic Redundancy Coding
(CRC) error detection is performed over the full 80 bits of the
received Q-channel subcode information in consumer mode, as
well as the full 192 bits of the received Channel Status informa-
tion in professional mode.
The AD1892 includes a SYNC input (Pin 23) that allows
multiple AD1892s in a system to be synchronized to a common
LEFT/
RIGHT
clock.
The AD1892 is offered in a 28-lead SOIC package. It operates
over the industrial temperature range from –40
°
C to +85
°
C
at a supply voltage from 4.5 V to 5.5 V. The only external
components required to support the AD1892 are power supply
decoupling capacitors.
DEFINITIONS
Dynamic Range
The ratio of a full-scale input signal to the integrated noise in the
passband (0 kHz to
≈
20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and
“60 dB” arithmetically added to the result. This measurement
technique is consistent with the recommendations of the Audio
Engineering Society (AES17-1991) and the Electronic Industries
Association of Japan (EIAJ CP-307).
Total Harmonic Distortion + Noise
Total Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the
values of the harmonics and noise to the value of the fundamen-
tal input frequency. It is usually expressed in percent (%) or
decibels.
Interchannel Phase Deviation
Difference in input sampling times between stereo channels,
expressed as a phase difference in degrees between 1 kHz inputs.
Group Delay
The time interval required for the frequency components of an
input pulse to appear at the converter’s output, expressed in
milliseconds (ms). More precisely, the derivative of radian phase
with respect to radian frequency at a given frequency.
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PDF描述 |
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| AD1892JRRL | Integrated Digital Receiver/Rate Converter |
| AD1892 | Integrated Digital Receiver/Rate Converter(數(shù)字音頻接收器/采樣率轉(zhuǎn)換器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1892JRRL | 制造商:Analog Devices 功能描述:Receiver/Rate Converter 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:INTEGRATED DIG.RECEIVER/RATE CONVERTER - Bulk |
| AD1892JRZ | 制造商:Analog Devices 功能描述:Receiver/Rate Converter 28-Pin SOIC W |
| AD1893 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter |
| AD1893JN | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W 制造商:Rochester Electronics LLC 功能描述:LOW COST ASRC PDIP 28-PIN - Bulk |
| AD1893JNZ | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W |
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