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參數(shù)資料
| 型號： | AD1892JR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Integrated Digital Receiver/Rate Converter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 231K |
| 代理商： | AD1892JR |
AD1892
REV. 0
–17–
LSB+2
LSB+1
MSB
MSB–1 MSB–2
RIGHT CHANNEL
LEFT CHANNEL
L
R
CLK
OUTPUT
BCLK
OUTPUT
SDATA
OUTPUT
MSB
MSB–1 MSB–2
LSB
LSB+2
LSB+1
LSB
LSB
Figure 27. Right-Justified Mode
RIGHT CHANNEL
LEFT CHANNEL
L
R
CLK
OUTPUT
BCLK
OUTPUT
SDATA
OUTPUT
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
MSB
Figure 28. I
2
S-Justified Mode
RIGHT CHANNEL
LEFT CHANNEL
L
R
CLK
OUTPUT
BCLK
OUTPUT
SDATA
OUTPUT
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
MSB
MSB+1
Figure 29. Left-Justified Mode
The incoming 16-bit CRC Word (Q82 through Q97) is routed
to the AD1892 CRC circuit block. The CRC block generates
a 16-bit polynomial against the first 80 bits of the incoming
Q-channel subcode and flags a CRC error if the generated CRC
is different from the incoming CRC (Q82 through Q97). Q-
Channel CRC errors are flagged in the AD1892 Status Register
1 in position D6.
An external microcontroller or microprocessor can use the
QDFS (Pin 6) output from the AD1892 as an interrupt to alert
the microcontroller that a new Q-Channel block is ready. When
the input sample rate is 44.1 kHz, the QDFS frequency is 75 Hz
([44,100
×
2]/1176 = 75).
OPERATING ISSUES
Serial Data Output Port
The AD1892 uses the frequency of the master clock (MCLK,
Pin 28) to determine the output sample rate. The LRCLK
signal is divided down from the master clock by a factor of 512.
The phase of this division can be adjusted by using the sync
input pin. The AD1892 is a clock master device; the audio data
clocks, bit clock (BCLK, Pin 26) and left/right clock are outputs
only. L
R
CLK runs continuously and transitions twice per stereo
sample period. BCLK also runs continuously and is used only to
clock the audio data from the AD1892’s serial data output port.
The AD1892’s flexible serial data output port transmits data in
twos-complement, MSB-first format. The left channel data
field always precedes the right channel data field. The output
data consists of 16 or 20 bits as established by settings in Con-
trol Register 1 (Bit D5). The BCLK frequency can be set
to either 32
×
F
SOUT
or 64
×
F
SOUT
(default) using Bit D1 in
Control Register 1.
Serial Output Port Modes
The AD1892 uses two bits in Control Register 1 to control the
mode configuration of the output data port. Bits D4 and D3
program the output data port mode as shown in Table III.
Table III. Serial Output Port Mode Control Bits
D4
D3
Serial Output Port Mode
I
2
S-Justified (See Figure 28) Default
Left-Justified (See Figure 29)
Right-Justified (See Figure 27)
Reserved
LO LO
LO HI
HI
HI
LO
HI
Note that in all three modes, the AD1892 is a “master” device,
i.e., the L
R
CLK, the BCLK and the SDATA signals are always
outputs. This is also true in bypass mode.
Figure 27 shows the right-justified mode. L
R
CLK is HI for the
left channel and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit out-
put mode) from an L
R
CLK transition, so that when there are
64 BCLK periods per L
R
CLK period, the LSB of the data will
be right-justified to the next L
R
CLK transition.
Figure 28 shows the default I
2
S-justified mode. When the AD1892
is used without a supporting microcontroller or microprocessor,
it will default to the I
2
S-justified mode after reset. L
R
CLK is
LO for the left channel and HI for the right channel. Data is
valid on the rising edge of BCLK. The MSB is left-justified to
an L
R
CLK transition but with a single BCLK period delay. The
I
2
S-justified mode can be used in either the 16-bit or the 20-bit
output mode.
Figure 29 shows the left-justified mode. L
R
CLK is HI for the
left channel and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left-justified to an L
R
CLK
transition with no MSB delay. The left-justified mode can be
used in the 16-bit or 20-bit output mode.
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| AD1892 | Integrated Digital Receiver/Rate Converter(數(shù)字音頻接收器/采樣率轉(zhuǎn)換器) |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD1892JRRL | 制造商:Analog Devices 功能描述:Receiver/Rate Converter 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:INTEGRATED DIG.RECEIVER/RATE CONVERTER - Bulk |
| AD1892JRZ | 制造商:Analog Devices 功能描述:Receiver/Rate Converter 28-Pin SOIC W |
| AD1893 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter |
| AD1893JN | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W 制造商:Rochester Electronics LLC 功能描述:LOW COST ASRC PDIP 28-PIN - Bulk |
| AD1893JNZ | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W |
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