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參數(shù)資料
| 型號： | AD1871YRSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC STEREO 24BIT 96KHZ 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 96k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極 |
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AD1871
–22–
REV. 0
Table VI. Control Register II (Address 0001b)
15–12
11
10
9
87
6
5
43
21
0
0001
0
MME
DF1
DF0
WW1
WW0
M/S
MUR
MUL
9–8
Reserved
7
MME
Modulator Mode Enable (0 = Normal Mode (Default), 1 = Mod Mode)
6–5
DF1–DF0
Data Format (See Table VIII)
4–3
WW1–WW0
Word Width (See Table VII)
2
M/S
Master/Slave Select (0 = Master Mode (Default); 1 = Slave Mode)
1
MUR
Mute Control, Right Channel (0 = Disabled (Default); 1 = Enabled)
0
MUL
Mute Control, Left Channel (0 = Disabled (Default); 1 = Enabled)
Table VII. Word-Width Settings
WW1
WW0
Word Width (No. of Bits)
00
24 (Default)
01
20
10
16
11
Reserved
Data Format
The AD1871’s serial data interface can be configured from a
choice of popular interface formats, including I2S, left-justified,
right-justified, or DSP Modes. Bits DF1–DF0 are programmed to
select the interface format (mode) as shown in Table VIII.
Table VIII. Data Interface Format Settings
*
DF1
DF0
Interface Mode
00I
2S (Default)
01
Right-Justified
10
DSP
11
Left-Justified
*Please refer to the Serial Data Interface section in the Functional
Description for more details on the various interface modes.
Modulator Mode Enable
The AD1871 defaults to the conversion of the analog audio to
linear, PCM-encoded digital outputs. Modulator Mode allows
the user to bypass the digital decimation filter section and access
the multibit sigma-delta modulator outputs directly. When in
this mode, certain pins are redefined (see Modulator Mode) and
the modulator output (at a nominal rate of 128
fS) is available
on the modulator data pins (D[0–3]). To enable the Modu-
lator Mode, set the MME Bit to high.
Modulator Clock
The modulator clock can be chosen to be either 128
fS or
64
fS. The AMC Bit (Bit 6) is used to select the modulator’s
clock rate. When AMC is set to 0 (default), the modulator clock
is 128
fS. Otherwise, if set to 1, the modulator clock is 64 fS.
This bit is normally set depending on whether the desired sampling
frequency is 48 kHz or 96 kHz and is also influenced by the
selected MCLK frequency. Please refer to the Functional
Description section for more information on MCLK selection
and sampling rates.
Power-Down
Power-down of the active clock signals within the AD1871 is
effected by writing a Logic 1 to Bit 7 (PD). In Power-Down
Mode, digital activity is suspended and analog sections are
powered down, with the exception of the reference.
High-Pass Filter
The AD1871’s digital filtering engine allows the insertion of a
high-pass filter (HPF) to effectively block dc signals from the
output digital waveform. Setting Bit 8 (HPE) enables the
high-pass filter. For more details of the HPF, refer to the
Functional Description section.
Peak Reading Enable
The AD1871 has two readback registers that can be enabled to
store the peak readings of the left and right channel ADC results.
To enable the peak readings to be captured, the Peak Reading
Enable Bit (PRE), Bit 9, must be set to Logic 1. When set to
Logic 0, the peak reading capture is disabled.
Control Register II
Control Register II contains bit settings for control of left/right
channel muting, data sample word width, data interface format,
and direct modulator bitstream output.
Mute Control
The left and right data channels can be muted to digital zero by
setting the MUL and MUR Bits (Bits 0 and 1), respectively. If a
channel is muted, its output data stream will remain at digital
zero, regardless of the amplitude of the input signal. Setting the
bit to 1 mutes the channel while setting the bit to 0 restores
normal operation.
Master/Slave Select
The AD1871 can operate as either a slave device or a master
device. In Slave Mode, the controller must provide the LRCLK
and BCLK to determine the sample rate and serial bit rate. In
Master Mode, the AD1871 provides the LRCLK and BCLK as
outputs that are applied to the controller. The AD1871 defaults to
Master Mode (
M/S is low) on reset.
Word Width
The AD1871 allows the output sample word width to be selected
from 16, 20, and 24 bits wide. Compact disc (CD) compatibility
may require 16 bits, while many modern digital audio formats
require 24-bit sample resolution. Bits WW1–WW0 are programmed
to select the word width. Table VII details the Control Register
Bit settings corresponding to the various word width selections.
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