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參數(shù)資料
| 型號(hào)： | AD1843JST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Serial-Port 16-Bit SoundComm Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 5/64頁 |
| 文件大?。?/td> | 848K |
| 代理商： | AD1843JST |
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AD1843
REV. 0
–5–
Figure 1. Timing Diagrams
ANALOG OUTPUT
Min
Typ
0.707
2.0
0.707
2.0
1.414
4.0
Max
Units
V rms
V p-p
V rms
V p-p
V rms
V p-p
k
k
k
%
dB
pF
pF
V
μ
A
k
mV
LOUT1 Full-Scale Output Voltage
(RMS Values Assume Sine Wave Input)
LOUT2 Full-Scale Single-Ended Output Voltage
(RMS Values Assume Sine Wave Input)
LOUT2 Full-Scale Differential Output Voltage
(RMS Values Assume Sine Wave Input)
LOUT1 Output Impedance*
LOUT2 Output Impedance*
LOUT1 External Load Impedance*
LOUT2 External Load Impedance*
MOUT External Load Impedance*
HPOUT External Load Impedance*
HPOUT THD+N (Referenced to Full Scale, 32
External Load Impedance)
1.8
2.2
1.8
2.2
3.6
4.4
600
1
10
2
10
16
32
0.10
–60
Output Capacitance*
External Load Capacitance*
CMOUT
External CMOUT Load Current*
CMOUT Output Impedance*
Mute Click* (Muted Output Minus Unmuted Midscale DAC1 and DAC2 Outputs)
15
100
2.40
10
2.10
2.25
4
±
5
SYSTEM SPECIFICATIONS
Max
1.0
±
1
5
Units
dB
Bit
Degrees
System Frequency Response Ripple* (Line-In to Line-Out)
Differential Nonlinearity*
Phase Linearity Deviation*
STATIC DIGITAL SPECIFICATIONS
Min
Max
Units
High-Level Input Voltage (V
IH
)
Digital Inputs, Except SCLK
XTALI and SCLK
Low-Level Input Voltage (V
IL
)
High-Level Output Voltage (V
OH
)
Low-Level Output Voltage (V
)
Input Leakage Current (GO/NOGO Tested)
Output Leakage Current (GO/NOGO Tested)
2.0
2.4
–0.3
2.4
V
DD
+ 0.3
V
DD
+ 0.3
0.8
V
V
V
V
V
μ
A
μ
A
0.4
10
10
–10
–10
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE AND DIGITAL SUPPLY RANGE)
Min
Typ
Max
Units
Serial Data Frame Sync [SDFS] Period (t
1
)
(Master Mode, FRS = 1 [16 Slots per Frame], SCF = 0 [SCLK = 12.288 MHz])
Frame Sync [SDFS] HI Pulse Width (t
)
Clock [SCLK] to Frame Sync [SDFS] Propagation Delay (t
PD1
)
Data [SDI] Input Setup Time to SCLK (t
S
)
Data [SDI] Input Hold Time from SCLK (t
)
Clock [SCLK] to Output Data [SDO] Valid (t
DV
)
Clock [SCLK] to Output Data [SDO] Three-State [High-Z] (t
HZ
)
Clock [SCLK] to Time Slot Output [TSO] Propagation Delay (t
PD2
)
RESET
and
PWRDWN
LO Pulse Width (t
RPWL
)
20.833
80
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
15
10
10
15
15
15
100
t
2
BIT 0
BIT 14
BIT 15
BIT 15
BIT 14
t
DV
BIT 0
t
PD1
SCLK
SDFS
SDI
SDO
t
S
t
H
t
HZ
RESET
PWRDWN
t
RPWL
151413
3 2 1 0 151413
LAST
TIVALID
t
PD2
t
PD1
SCLK
SDFS
SDI OR SDO
TSO
t
1
151413
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