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參數(shù)資料
| 型號： | AD1836AZ-DBRD |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD1836A |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 音頻編解碼器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD1836A |
| 主要屬性： | 3 個立體聲 DAC -95 dB THD + N，108 dB SNR，2 個立體聲 ADC -92 dB THD + N，105 dB SNR |
| 次要屬性： | 接受 16/18/20/24 位數(shù)據(jù)，SPI 接口，支持 48 或 96 kHz 采樣率 |
| 已供物品： | 板 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD1836ACSZ-ND - IC CODEC 4ADC/6DAC 24 BIT 52MQFP AD1836AASZRLTR-ND - IC CODEC 4ADC/6DAC 24 BIT 52MQFP AD1836AASZ-ND - IC CODEC 4ADC/6DAC 24 BIT 52MQFP |
AD1836A
Data Sheet
Rev. A | Page 18 of 24
Table 11. Pin Function Changes in AUX Mode
Pin Name (I2S/AUX Mode)
I2S Mode
AUX Mode
ASDATA1(O)
I2S Data Out, Internal ADC1
TDM Data Out, to SHARC
ASDATA2(O)/DAUXDATA(O)
I2S Data Out, Internal ADC2
AUX—I2S Data Out (to External DAC)
DSDATA1(I)
I2S Data In, Internal DAC1
TDM Data In, from SHARC
DSDATA2(I)/AAUXDATA(I)
I2S Data In, Internal DAC2
AUX—I2S Data In 1 (to External ADC)
DSDATA3(I)/AAUXDATA2(I)
I2S Data In, Internal DAC3
AUX—I2S Data In 2 (to External ADC)
ALRCLK(O)
LRCLK for Internal ADC1, ADC2
TDM Frame Sync Out, to SHARC
ABCLK(O)
BCLK for Internal ADC1, ADC2
TDM BCKL Out, to SHARC
DLRCLK(I)/AUXLRCLK(I/O)
LRCLK In/Out Internal DACs
AUX LRCLK In/Out, Driven by External IRCLK from ADC (in slave mode).
In master mode, driven by internal MCLK/512.
DBCLK(I)/AUXBCLK(I/O)
BCLK In/Out Internal DACs
AUX BCLK In/Out, Driven by External BCLK from ADC (in slave mode).
In master mode, driven by internal MCLK/8.
AUXDATA1
ASDATA2/DAUXDATA
DATA TO EXT DAC
BCLK AND LRCLK FOR
EXT DAC COMES FROM
ADC BCLK, LRCLK.
MUST BE IN I2S MODE.
ADC
SYNC SIGNAL DERIVED FROM AUXLRCLK USED TO
RESET INTERNAL ADC COUNTER
ASDATA1
AUXDATA
I2S FORMATTER
MUX
AUXLRCLK
2 AUX
CHANNELS
6-CH
DAC
6 MAIN
CHANNELS
DAC
SPORT
DSDATA1
DSDATA2
DSDATA3
LRCLK
BCLK
SPORT
SYNC
4 ADCS
AUXBCLK
AUXLRCLK
AUXDATA2
I2S
DECODE
LRCLK
ABCLK
ASDATA1
ALRCLK
ABCLK
ASDATA1
DATA TO SHARC
INDICATES MUX POSITION FOR AUX-TDM MODE
MASTER/SLAVE MODE,
FROM ADC SPI PORT
FROM SHARC
FROM EXT A/D
DSDATA1
DSDATA2/AUXDATA1
DSDATA3/AUXDATA2
DLRCLK/AUXLRCLK
MCLK
TIMING GEN
LRCLK BCLK
DBCLK/AUXBCLK
MUX
AUXBCLK
MUX
I2S
Figure 12. Extended TDM Mode (Internal Flow Diagram)
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