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參數(shù)資料
| 型號： | AD1821 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | MODIO(Modem over Audio) SoundComm Host Signal Processing Codec(音頻調(diào)制SoundComm型主信號處理編解碼器) |
| 中文描述： | MODIO（調(diào)制解調(diào)器多音頻）SoundComm主機信號處理編解碼器（音頻調(diào)制SoundComm型主信號處理編解碼器） |
| 文件頁數(shù)： | 18/44頁 |
| 文件大小： | 284K |
| 代理商： | AD1821 |
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AD1821
–18–
REV. 0
SSPVI
SS/SB Playback Substitution Data Input Valid Flag. T his bit is ignored if: (1) Intercept mode is not enabled for
SS/SB playback or (2) T he AD1821 did not request data for SS/SB playback in the previous frame (see the
SSPRQ bit in the Status Word Output). Otherwise, setting this bit indicates that Slots 4 and 5 contain valid right
and left SS/SB playback substitution data. If in “capture rate equal to playback rate” mode, setting this bit also in-
dicates that valid capture substitution data is being sent to the AD1821. If not in modem mode, right and left
channel capture substitution data is accepted in Slots 2 and 3 respectively. If in modem mode, only mono capture
substitution data is accepted in slots 2 and 3. When this bit is cleared, data in all slots controlled by this bit, as de-
fined above, is ignored.
SS/SB Capture Substitution Data Input Valid Flag. T his bit is ignored if: (1) Intercept mode is not enabled for SS/
SB capture or (2) T he AD1821 did not request data for SS/SB capture in the previous frame (see the SSCRQ bit
in the Status Word Output). Otherwise, setting this bit indicates that valid SS/SB capture substitution data is being
sent to the AD1821. If not in modem mode, or DSP port or ISA bus based, right and left channel capture data is
accepted in Slots 2 and 3 respectively. If in modem mode, only mono capture substitution data is accepted in Slot
3, because Slot 2, which is mapped to the right capture channel, is being used for modem. T his mono data will,
however, be sent to both left and right ISA SS/SB capture channels. When this bit is cleared, data in Slots 3 and 2
is ignored.
Reserved: T o ensure future compatibility write “0” to all reserved bits.
DSP Port Clear Status Flag. When this bit is set, (write 1), the PNPR and PDN flag bits in the status word (Bits
15 and 14 of slots 0 SDO) are cleared. When this bit is cleared, (writing a 0), it has no effect on PNPR and PDN
and preserves them in the previous states.
SSCVI
RES
FCLR
Status Word Output (Slot 0 SDO)
15
14
13
RES
5
RES
12
11
10
9
8
PD N
7
MB1
PNPR
6
MB0
SSCVO
4
SSCRQ
SSPVO
3
SSPRQ
FMVO
2
FMRQ
IS1VO
1
IS1RQ
IS0VO
0
IS0RQ
IS0RQ
I
2
S Port (0) Input Request Flag. T his bit is set if intercept mode is enabled for I
2
S Port (0) and its four-word
stereo input buffer is not full.
I
2
S Port (1) Input Request Flag. T his bit is set if intercept mode is enabled for I
2
S Port (1) and its four-word
stereo input buffer is not full.
FM Synthesis Input Request Flag. T his bit is set if intercept mode is enabled for FM synthesis and its four-word
stereo input buffer is not full.
SS/SB Capture Input Request Flag. T his bit is set if intercept mode is enabled for SS/SB playback and its four-
word stereo input buffer is not full.
SS/SB Capture Input Request Flag. T his bit is set if intercept mode is enabled for SS/SB capture and its
four-word stereo input buffer is not full.
Mailbox 0 Status Flag. T his bit is set if the most recent action to SS indirect register 42 (DSP port Mail Box 1)
was a write, and is cleared if the most recent action was a read. T he status of this bit is also reflected in SS indirect
register 33. It may be used as a handshake bit to facilitate communication between a DSP on the DSP port and a
host CPU on the ISA bus.
Mailbox 1 Status Flag. T his bit is set if the most recent action to SS indirect register 43 (DSP port Mail Box 1)
was a write and is cleared if the most recent action was a read. T he status of this bit is also reflected in SS indirect
register 33. It may be used as a handshake bit to facilitate communication between a DSP on the DSP port and a
host CPU on the ISA bus.
I
2
S Port 0 Valid Out. T his bit is set if Slots 10 and 11 contain valid right and left I
2
S Port 0 data.
I
2
S Port 1 Valid Out. T his bit is set if Slots 8 and 9 contain valid right and left I
2
S Port 1 data.
FM Synthesis Valid Out. T his bit is set if Slots 6 and 7 contain valid left and right FM synthesis data.
SS/SB Playback Valid Out. T his bit is set if Slots 4 and 5 contain valid right and left SS/SB playback data.
SS/SB Capture Valid Out. T his bit is set if valid SS/SB capture data is being transmitted. If not in a modem mode,
Slots 2 and 3 will contain valid right and left SS/SB capture data. If in modem mode, only Slot 3 will contain valid
left SS/SB capture data as Slot 2 and the ADC right channel are used by the modem.
IS1RQ
FMRQ
SSPRQ
SSCRQ
MB0
MB1
IS0VO
IS1V1
FMVO
SSPVO
SSCVO
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