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參數(shù)資料
| 型號： | AD1817A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multimedia Audio Subsystem For Concurrently Processing Multiple Digital Streams Of 16-bit Stereo Audio In Personal Computers.(可處理個人電腦的16位立體聲多重數(shù)字流的多媒體聲音子系統(tǒng)) |
| 中文描述： | 多媒體音頻子系統(tǒng)，為同時處理中的16多個數(shù)字信息流，在個人電腦。位立體聲音頻（可處理個人電腦的16位立體聲多重數(shù)字流的多媒體聲音子系統(tǒng)） |
| 文件頁數(shù)： | 31/44頁 |
| 文件大小： | 269K |
| 代理商： | AD1817A |
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AD1817A
–31–
REV. 0
PRELIMINARY
4
3
2
1
RES
TECHNICAL
0
[40] RE SE RVE D
7
DE FAULT = 0x0000
2
1
6
5
RES
4
3
2
1
0
7
6
5
4
3
0
RES
[41] HARD WARE VOL UME BUT T ON MOD IF IE R
7
6
5
4
D E F AUL T = [0xX X 1B]
2
3
2
1
0
7
6
5
4
3
1
0
HVM
HVSEL
HVMAS
HVAT N [4:0]
VMU
VUP
VDN
BM [4:0]
BM [4:0] Button Modifier
Volume Down
Volume Up
Volume Mute
Hardware Volume Attenuation
Hardware Volume Master Mode
Hardware Volume Select
Hardware Volume Mute
VDM
VUP
VMU
HVAT N [4:0]
HVMAS
HVSEL
HVM
T his register contains a Master Volume attenuation offset, which can be incremented or decremented via the Hardware Volume
Pins. T his register is summed with the Master Volume attenuation to produce the actual Master Volume DAC attenuation. A mo-
mentary grounding of greater than 50 ms on the VOL_UP pin will cause a decrement (decrease in Attenuation) in this register.
Holding the pin LO for greater than 200 ms will cause an auto-decrement every 200 ms. T his is also true for a momentary ground-
ing of the VOL_DN pin. A momentary grounding of both the VOL_UP and VOL_DN causes a mute and no increment or decre-
ment to occur.
When Muted, an unmute is possible by a momentary grounding of both the VOL_UP and VOL_DN pins together, a momen-
tary grounding of VOL_UP (this also causes a volume increase), a momentary grounding of VOL_DN (this also causes a volume
decrease) or a write of “0” to the VI bit in SS [BASE+1].
[42] RE SE RVE D
7
DE FAULT = [0x0000]
2
6
5
4
3
2
1
0
7
6
5
4
3
1
0
RES
RES
[43] RE SE RVE D
7
DE FAULT = [0x0000]
2
6
5
7
6
5
4
3
1
0
RES
[44] POWE R-DOWN AND T IME R C ONT ROL
7
6
5
C PD
RES
PIW
PIR
DE F AUL T = [0x0000]
2
1
RES
4
3
2
1
0
7
6
5
4
3
0
PAA
PDA
RES
PT B
G PSP
T he AD1817A supports a timeout mechanism used in conjunction with the T imer Base Count and T imer Current Count registers
to generate a power-down interrupt. T his interrupt allows software to power down the entire chip by setting the CPD bit. T his
power-down control feature lets users program a time interval from 1 ms to approximately 1.8 hours in 1 ms increments. Five
power-down count reload enable bits are used to reload the T imer Current Count from the T imer Base Count when activity is
seen on that particular channel.
Programming Example: Generate Interrupt if No ISA Reads or Writes occur within 15 Minutes.
1) Write [SSBASE+0] with 0x0C ; Write Indirect address for T IMER BASE COUNT “register 12”
2) Write [SSBASE+2] with 0x28 ; Write T IMER BASE COUNT with (15 min
×
60 sec/min
×
10) = 0x2328 mili-Seconds
3) Write [SSBASE+3] with 0x23 ; Write High byte of T IMER BASE COUNT
4) Write [SSBASE+0] with 0x2C ; Write Indirect address for POWER-DOWN and T IMER CONT ROL register
5) Write [SSBASE+2] with 0x00 ; Write Low byte of POWER-DOWN and T IMER CONT ROL register
6) Write [SSBASE+3] with 0x30 ; Set Enable bits for PIW & PIR
7) Write [SSBASE+0] with 0x01 ; Write Indirect address for INT ERRUPT CONFIG register
8) Write [SSBASE+2] with 0x82 ; Set the T E (T imer Enable) bit
9) Write [SSBASE+3] with 0x20 ; Set the T IE (T imer Interrupt Enable) bit
GPSP
Game Port Speed Select. Selects the operating speed of the game port.
0
Slow Game Port
1
Fast Game Port
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