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參數(shù)資料
| 型號： | AD1817A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multimedia Audio Subsystem For Concurrently Processing Multiple Digital Streams Of 16-bit Stereo Audio In Personal Computers.(可處理個人電腦的16位立體聲多重數(shù)字流的多媒體聲音子系統(tǒng)) |
| 中文描述： | 多媒體音頻子系統(tǒng)，為同時處理中的16多個數(shù)字信息流，在個人電腦。位立體聲音頻（可處理個人電腦的16位立體聲多重數(shù)字流的多媒體聲音子系統(tǒng)） |
| 文件頁數(shù)： | 28/44頁 |
| 文件大?。?/td> | 269K |
| 代理商： | AD1817A |
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AD1817A
–28–
REV. 0
TECHNICAL
[08] PLAY BAC K BASE C OUNT
7
6
DE FAULT = [0x0000]
2
5
4
3
2
1
0
7
6
5
4
PBC [7:0]
3
1
0
PBC [15:8]
PBC [15:0]
Playback Base Count. T his register is for loading the Playback DMA Count. Writing a value to this register also
loads the same data into the Playback Current Count register. You must load this register when Playback Enable
(PEN) is deasserted. When PEN is asserted, the Playback Current Count decrements once for every four bytes
transferred via a DMA cycle. T he next transfer, after zero is reached in the Playback Current Count, will gener-
ate an interrupt and reload the Playback Current Count with the value in the Playback Base Count. T he Playback
Base Count should always be programmed to Number Bytes divided by four, minus one ((Number Bytes/4) –1).
T he circular software DMA buffer must be divisible by four to ensure proper operation.
[09] PLAY BAC K C URRE NT C OUNT
7
6
5
DE FAULT = [0x0000]
2
4
3
2
1
0
7
6
5
4
3
1
0
PCC [15:8]
PCC [7:0]
PCC [15:0]
Playback Current Count register. Contains the current Playback DMA Count. Reads and Writes must be done
when PEN is deasserted.
[10] C APT URE BASE C OUNT
7
6
DE F AUL T = [0x0000]
2
5
4
3
2
1
0
7
6
5
4
3
1
0
CBC [15:8]
CBC [7:0]
CBC [15:0]
Capture Base Count. T his register is for loading the Capture DMA Count. Writing a value to this register also
loads the same data into the Capture Current Count register. Loading must be done when Capture Enable
(CEN) is deasserted. When CEN is asserted, the Capture Current Count decrements once for every four bytes
transferred via a DMA cycle. T he next transfer, after zero is reached in the Capture Current Count, will generate
an interrupt and reload the Capture Current Count with the value in the Capture Base Count. T he Capture Base
Count should always be programmed to Number Bytes divided by four, minus one ((Number Bytes/4) –1). T he
circular software DMA buffer must be divisible by four to ensure proper operation.
[11] C APT URE C URRE NT C OUNT
7
6
5
DE F AUL T = [0x0000]
2
4
3
2
1
0
7
6
5
4
3
1
0
CCC [15:8]
CCC [7:0]
CCC [15:0]
Capture Current Count register. Contains the current Capture DMA Count. Reading and Writing must be done
when CEN is deasserted.
[12] T IME R BASE C OUNT
7
6
DE F AUL T = [0x0000]
2
5
4
3
2
1
0
7
6
5
4
3
1
0
T BC [15:8]
T BC [7:0]
T BC [15:0]
T imer Base Count. Register for loading the T imer Count. Writing a value to this register also loads the same data
into the T imer Current Count register. Loading must be done when T imer Enable (T E) is deasserted. When T E
is asserted, the T imer Current Count register decrements once for every specified time period. T he time period
(10
μ
s or 100 ms) is programmed via the PT B bit in SS [44]. When T E is asserted, the T imer Current Count decre-
ments once every time period. T he next count, after zero is reached in the T imer Current Count register, will generate
an interrupt and reload the T imer Current Count register with the value in the T imer Current Count register.
[13] T IME R C URRE NT C OUNT
7
6
DE FAULT = [0x0000
]
2
5
4
3
2
1
0
7
6
5
4
3
1
0
T CC [15:8]
T CC [7:0]
T CC [15:0]
T imer DMA Current Count register. Contains the current timer count. Reading and Writing must be done when
T E is deasserted.
[14] MAST E R VOL UME AT T E NUAT ION
7
6
5
LMVM
RES
DE F AUL T = [0x8888]
2
1
RMVA [4:0]
4
3
2
1
0
7
6
5
4
3
0
LMVA [4:0]
RMVM
RES
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