參數資料
| 型號： | AD1380KD |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC SNGL 16BIT 32-CDIP |
| 標準包裝： | 1 |
| 位數： | 16 |
| 采樣率（每秒）： | 50k |
| 數據接口： | 并聯(lián) |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 900mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-DIP（0.900"，22.86mm） |
| 供應商設備封裝： | 32-BBDIP-H |
| 包裝： | 管件 |
| 輸入數目和類型： | 16 個單端，雙極；16 個單端，單極 |
AD1380
Rev. D | Page 8 of 12
DIGITAL OUTPUT DATA
INPUT SCALING
Parallel data from TTL storage registers is in negative true form
(Logic 1 = 0 V and Logic 0 = 2.4 V). Parallel data output coding
is complementary binary for unipolar ranges and comple-
mentary offset binary for bipolar ranges. Parallel data becomes
valid at least 20 ns before the STATUS flag returns to Logic 0,
permitting parallel data transfer to be clocked on the 1 to 0
transition of the STATUS flag (see
The AD1380 inputs should be scaled as close to the maximum
input signal range as possible to use the maximum signal
resolution of the ADC. Connect the input signal as shown in
00764-008
8
ANALOG
COMMON
4
BIPOLAR
OFFSET
COMPARATOR
IN
7
6
5
7.5k
Ω
R2
3.75k
Ω
10V SPAN
20V SPAN
R1
3.75k
Ω
FROM DAC
COMPARATOR
TO
SAR
VREF
Figure 7). Parallel data
output changes state on positive going clock edges.
00764-007
BIT 16
VALID
BUSY
(STATUS)
20ns MIN TO 90ns
Figure 7. LSB Valid to Status Low
Figure 8. Input Scaling Circuit
Table 3. Input Scaling Connections
Connect Input
Signal to
Input Signal Line
Output Code
Connect Pin 4 to
Connect Pin 7 to
Connect Pin 32 to
±10 V
COB
Pin 51
Pin 32
Pin 31
Pin 7
±5 V
COB
Pin 51
Open
Pin 31
Pin 6
±2.5 V
COB
Pin 51
Pin 31
Pin 6
0 V to +5 V
CSB
Open
Pin 51
Pin 31
Pin 6
0 V to +10 V
CSB
Open
Pin 31
Pin 6
Pin 5 is extremely sensitive to noise and should be guarded by ANALOG COMMON.
1
Table 4. Transition Values vs. Calibration Codes
Output Code
MSB
Range
±10 V
±5 V
±2.5 V
0 V to +10 V
0 V to +5 V
000. . . .0002
+Full Scale
+10 V
+5 V
+2.5 V
+10 V
+5 V
3/2 LSB
011 . . . 111
Midscale
0 V
+5 V
+2.5 V
1/2 LSB
111 . . . 110
Full Scale
10 V
5 V
2.5 V
0 V
+1/2 LSB
For LSB value for range and resolution used, see Table 5.
1
Voltages given are the nominal value for transition to the code specified.
2
Table 5. Input Voltage Range and LSB Values
Analog Input Voltage Range
±10 V
±5 V
±2.5 V
0 V to +10 V
0 V to +5 V
Code Designation
n
2
V
20
n
2
V
10
n
2
V
10
n
2
V
5
n
2
V
5
n
2
FSR
One Least Significant Bit (LSB)
n = 8
78.13 mV
39.06 mV
19.53 mV
39.06 mV
19.53 mV
n = 10
19.53 mV
9.77 mV
4.88 mV
9.77 mV
4.88 mV
n = 12
4.88 mV
2.44 mV
1.22 mV
2.44 mV
1.22 mV
n = 13
2.44 mV
1.22 mV
0.61 mV
1.22 mV
0.61 mV
n = 14
1.22 mV
0.61 mV
0.31 mV
0.61 mV
0.31 mV
n = 15
0.61 mV
0.31 mV
0.15 mV
0.31 mV
0.15 mV
1 COB = complementary offset binary.
2 CTC = complementary twos complement—achieved by using an inverter to complement the most significant bit to produce MSB.
3 CSB = complementary straight binary.
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