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參數(shù)資料
| 型號： | AD1377KD |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC SNGL 16BIT 32-CDIP |
| 標準包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 111k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-DIP（0.900"，22.86mm） |
| 供應商設備封裝： | 32-BBDIP-H |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 16 個單端，雙極；16 個單端，單極 |
AD1376/AD1377
Rev. D | Page 6 of 12
DESCRIPTION OF OPERATION
0.0135
0.0080
0.0195
0.0120
0
–0.0120
–0.0195
0.0060
0.0030
0
–0.0030
–0.0060
–0.0080
–0.0135
025
70
00699-002
TEMPERATURE (
°C)
LINE
ARITY
E
RRO
R
(%
FS
R)
AD1376/AD1377KD
±2ppm/°C,
±0.003%, @ 25°C
AD1376/AD1377JD
±3ppm/°C,
±0.006%, @ 25°C
Figure 2. Linearity Error vs. Temperature
0.100
AD1376
0.001
0.003
0.006
0.010
5
10152
00699-003
CONVERSION TIME (
s)
LINE
ARITY
AND
DIFFE
RE
NTIAL
LINE
ARITY
E
RROR
(%
OF
FS
R)
0
SHORT CYCLED TO 12 BITS
1/2LSB 12-BIT
1/2LSB 13-BIT
1/2LSB 14-BIT
SHORT CYCLED TO 13 BITS
SHORT CYCLED TO 14 BITS
Figure 3. AD1376 Nonlinearity vs. Conversion Time
0.100
0.038
–0.038
0
–0.068
0.068
0
–0.100
0
60
50
40
30
20
10
00699-004
70
G
A
IN
DRIFT
E
RRO
R
(%
FS
R)
Figure 4. Gain Drift Error vs. Temperature
On receipt of a CONVERT START command, the AD1376/
AD1377 convert the voltage at the analog input into an
equivalent 16-bit binary number. This conversion is
accomplished as follows: the 16-bit successive approximation
register (SAR) has its 16-bit outputs connected both to the
device bit output pins and to the corresponding bit inputs of the
feedback DAC. The analog input is successively compared to
the feedback DAC output, one hit at a time (MSB first, LSB
last). The decision to keep or reject each bit is then made at the
completion of each bit comparison period, depending on the
state of the comparator at that time.
GAIN ADJUSTMENT
The gain adjustment circuit consists of a 100 ppm/°C poten-
tiometer connected across ±VS with its slider connected
through a 300 k resistor to Pin 29 (GAIN ADJ) as shown in
If no external trim adjustment is desired, Pin 27
(COMPARATOR IN) and Pin 29 can be left open.
00699-005
AD1376/AD1377
29
0.01
F
300k
+15V
10k
TO
100k
100ppm/
°C
–15V
Figure 5. Gain Adjustment Circuit (±0.2% FSR)
ZERO OFFSET ADJUSTMENT
The zero offset adjustment circuit consists of a 100 ppm/°C
potentiometer connected across ±VS with its slider connected
through a 1.8 M resistor to Pin 27 for all ranges. As shown in
Figure 6, the tolerance of this fixed resistor is not critical; a carbon
composition type is generally adequate. Using a carbon compo-
sition resistor having a 1200 ppm/°C temperature coefficient
contributes a worst-case offset temperature coefficient of 32 LSB14
× 61 ppm/LSB14 × 1200 ppm/°C = 2.3 ppm/°C of FSR, if the offset
adjustment potentiometer is set at either end of its adjustment
range. Since the maximum offset adjustment required is typically
no more than ±16 LSB14, use of a carbon composition offset
summing resistor typically contributes no more than 1 ppm/°C of
FSR offset temperature coefficient.
00699-006
AD1376/AD1377
27
1.8M
+15V
10k
TO
100k
–15V
Figure 6. Zero Offset Adjustment Circuit (±0.3% FSR)
An alternate offset adjustment circuit, which contributes a
negligible offset temperature coefficient if metal film resistors
(temperature coefficient <100 ppm/°C) are used, is shown in
00699-007
AD1376/AD1377
27
22k
M.F.
180k
M.F. 180k M.F.
+15V
10k
TO
100k
OFFSET
ADJ
–15V
Figure 7. Low Temperature Coefficient Zero Adjustment Circuit
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