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參數(shù)資料
| 型號(hào)： | AD1377KD |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC SNGL 16BIT 32-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 111k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-DIP（0.900"，22.86mm） |
| 供應(yīng)商設(shè)備封裝： | 32-BBDIP-H |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 16 個(gè)單端，雙極；16 個(gè)單端，單極 |
AD1376/AD1377
Rev. D | Page 9 of 12
Table 5. Transition Values vs. Calibration Codes
Output Code
MSB
LSB1
Range
±10 V
±5 V
±2.5 V
0 V to +10 V
0 V to +5 V
000 ………0002
+Full Scale
+10 V
+5 V
+2.5 V
+10 V
+5 V
3/2 LSB
011………111
Midscale
0 V
+5 V
+2.5 V
–1/2 LSB
111………110
Full Scale
10 V
5 V
2.5 V
0 V
+1/2 LSB
1 For LSB value for range and resolution used, see Ta
.
ble 6
Table 6. Input Voltage Range and LSB Values
2 Voltages given are the nominal value for transition to the code specified.
Analog Input Voltage Range
±10 V
±5 V
±2.5 V
0 V to +10 V
0 V to +5 V
Code Designation
COB1 or CTC2
COB1 or CTC2
CSB3
One Least Significant Bit (LSB)
n
2
FSR
n
2
V
20
n
2
V
10
n
2
V
5
n
2
V
10
n
2
V
5
n = 8
78.13 mV
39.06 mV
19.53 mV
39.06 mV
19.53 mV
n = 10
19.53 mV
9.77 mV
4.88 mV
9.77 mV
4.88 mV
n = 12
4.88 mV
2.44 mV
1.22 mV
2.44 mV
1.22 mV
n = 13
2.44 mV
1.22 mV
0.61 mV
1.22 mV
0.61 mV
n = 14
1.22 mV
0.61 mV
0.31 mV
0.61 mV
0.31 mV
n = 15
0.61 mV
0.31 mV
0.15 mV
0.31 mV
0.15 mV
1 COB = complementary offset binary.
2 CTC = complementary twos complement—achieved by using an inverter to complement the most significant bit to produce MSB.
3 CSB = complementary straight binary
Zero- and full-scale calibration can be accomplished to a
precision of approximately ±1/2 LSB using the static adjustment
procedure described previously. By summing a small sine or
triangular wave voltage with the signal applied to the analog
input, the output can be cycled through each of the calibration
codes of interest to more accurately determine the center (or
end points) of each discrete quantization level. A detailed
description of this dynamic calibration technique is presented
in Analog-Digital Conversion Handbook, edited by D. H.
Sheingold, Prentice Hall, Inc., 1986.
GROUNDING, DECOUPLING, AND LAYOUT
CONSIDERATIONS
Many data acquisition components have two or more ground
pins that are not connected together within the device. These
grounds are usually referred to as DIGITAL COMMON (logic
power return), ANALOG COMMON (analog power return), or
analog signal ground. These grounds (Pin 19 and Pin 22) must
be tied together at one point as close as possible to the
converter. Ideally, a single solid analog ground plane under the
converter would be desirable. Current flows through the wires
and etch stripes of the circuit cards, and since these paths have
resistance and inductance, hundreds of millivolts can be
generated between the system analog ground point and the
ground pins of the ADC. Separate wide conductor stripe
ground returns should be provided for high resolution
converters to minimize noise and IR losses from the current
flow in the path from the converter to the system ground point.
In this way, ADC supply currents and other digital logic-gate
return currents are not summed into the same return path as
analog signals where they would cause measurement errors.
Each of the ADC supply terminals should be capacitively
decoupled as close to the ADC as possible. A large value (such
as 1 F) capacitor in parallel with a 0.1 F capacitor is usually
sufficient. Analog supplies are to be bypassed to the ANALOG
COMMON (analog power return) Pin 22 and the logic supply is
bypassed to DIGITAL COMMON (logic power return) Pin 19.
The metal cover is internally grounded with respect to the
power supplies, grounds, and electrical signals. Do not
externally ground the cover.
CLOCK RATE CONTROL
The AD1376/AD1377 can be operated at faster conversion
times by connecting the clock rate control (Pin 23) to an
external multiturn trim potentiometer (TCR <100 ppm/°C) as
shown in Figure 13.
00699-013
AD1376/AD1377
23
2.25MHz @ 5V
1750kHz @ DGND
15V DC
5k
Figure 13. Clock Rate Control Circuit
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