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參數(shù)資料
| 型號： | AD10265AZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LJT 10C 10#20 SKT RECP |
| 中文描述： | DUAL 3-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, LCC-68 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 267K |
| 代理商： | AD10265AZ |
Test
Level
Mil
Subgroup
AD10265AZ
Typ
Parameter
Temp
Min
Max
Units
SPURIOUS-FREE DYNAMIC RANGE
9
Analog Input
@ 1.24 MHz
+25
°
C
Full
+25
°
C
Full
+25
°
C
Full
I
II
I
II
I
II
4
5, 6
4
5, 6
4
5, 6
75
75
72
72
72
72
80
80
80
79
79
79
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
@ 17 MHz
@ 32 MHz
TWO-TONE IMD REJECTION
10
f1, f2 @ –7 dBFS
Full
II
4, 5, 6
72
80
dBc
CHANNEL-TO-CHANNEL ISOLATION
11
+25
°
C
IV
12
80
dB
LINEARITY
Differential Nonlinearity
(Encode = 20 MHz)
Integral Nonlinearity
(Encode = 20 MHz)
+25
°
C
IV
12
–1.0
±
0.5
1.5
LSB
Full
V
±
1.25
LSB
DIGITAL OUTPUTS
Logic Compatibility
Logic “1” Voltage
Logic “0” Voltage
Output Coding
CMOS
DV
CC
– 0.2
0.2
Full
Full
I
I
1, 2, 3
1, 2, 3
2.8
V
V
0.5
Twos Complement
POWER SUPPLY
AV
CC
Supply Voltage
I (AV
CC
) Current
AV
EE
Supply Voltage
I (AV
EE
) Current
DV
CC
Supply Voltage
I (DV
CC
) Current
I
CC
(Total) Supply Current
Power Dissipation (Total)
Power Supply Rejection Ratio (PSRR)
Full
Full
Full
Full
Full
Full
Full
Full
Full
VI
V
VI
V
VI
V
I
I
IV
+5.0
336
–5.0
66
+3.3
20
422
2.1
0.01
V
mA
V
mA
V
mA
mA
W
% FSR/% V
S
1, 2, 3
1, 2, 3
7, 8
520
2.4
0.02
NOTES
1
Gain tests are performed on A
IN
1 over specified input voltage range.
2
Input capacitance specifications show only ceramic package capacitance.
3
Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4
ENCODE driven by single-ended source;
ENCODE
bypassed to ground through 0.01
μ
F capacitor.
5
ENCODE may also be driven differentially in conjunction with
ENCODE
; see “Encoding the AD10265” for details.
6
Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50%
±
5%.
7
Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 65 MSPS.
8
Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS.
9
Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur.
10
Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod product. f1 = 17.0 MHz
±
100 kHz, f2 = 18.0 MHz
±
100 kHz.
11
Channel-to-channel isolation tested with A channel/50 ohm terminated <A
IN
2 grounded, and a full-scale signal applied to B channel (A
IN
1).
All specifications guaranteed within 100 ms of initial power up regardless of sequencing.
Specifications subject to change without notice.
AD10265
–3–
REV. 0
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