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參數(shù)資料
| 型號： | A65H83181 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output |
| 中文描述： | 128K的× 36 |
| 文件頁數(shù)： | 14/21頁 |
| 文件大?。?/td> | 530K |
| 代理商： | A65H83181 |
A65H73361/A65H83181 Series
PRELIMINARY
(February, 1999, Version 2.0)
13
AMIC Technology, Inc.
IEEE 1149.1 TAP AND BOUNDARY SCAN
The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os and printed
circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core.
In conformance with IEEE std. 1149.1, the SRAM contains a TAP controller, Instruction register, Boundary Scan register,
Bypass register and ID register.
The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not
required.
Signal List
l
TCK : Test Clock
l
TMS : Test Mode Select
l
TDI : Test Data In
l
TDO : Test Data Out
Caution:
TCK, TMS, TDI must be tied down, even if JTAG is not used.
JTAG Recommended DC Operating Conditions
(T
J
= 0 to 110
°
C)
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
JTAG Input High Voltage
V
IH1
2.2
-
V
DD
+ 0.3
V
1
JTAG Input Low Voltage
V
IL1
-03
-
0.8
V
1
JTAG Output High Level
V
OH1
2.4
-
-
V
1,2
JTAG Output Low Level
V
OL1
-
-
0.4
V
1,3
1. All JTAG Inputs/Outputs are LVTTL Compatible only.
2. I
OH1
= -8mA at 2.4V.
3. I
OL1
= +8mA at 0.4V.
JTAG Recommended DC Operating Conditions
(T
J
= 0 to 110
°
C)
Parameter
Symbol
Conditions
Units
Notes
Input Pulse High Level
V
IH1
3.0
V
Input Pulse Low Level
V
IL1
0.0
V
Input Rise Time
T
R1
2.0
ns
Input Fall Time
T
F1
2.0
ns
Input and Output Timing Reference Level
1.5
V
1
1. See AC Test Loading on page 8.
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| A65H83181P-5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output |
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