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參數(shù)資料
| 型號(hào)： | A64S9316G-85 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 512K X 16 Bit Low Voltage Super RAM |
| 中文描述： | 為512k × 16位低電壓超內(nèi)存 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 171K |
| 代理商： | A64S9316G-85 |
A64S9316
PRELIMINARY
(July, 2002, Version 0.1)
12
AMIC Technology, Inc.
Timing Waveforms (continued)
Write Cycle 3-1
(6)
(Byte Enable Controlled)
t
SKEW
t
WC
t
WC
t
SKEW
t
ASC
t
CEH
t
ASC
Address
CE1
HB,
t
AW
t
CW
t
AW
t
CW
t
BW
2
t
WP
t
DW
t
DH
t
WHZ
4
t
OW
t
WP
t
WHZ
4
t
DH
t
DW
t
OW
WE
Data In
Data Out
t
AHC
t
AHC
t
BW
2
t
WR
3
t
WR
3
t
AS
1
t
AS
1
Write Cycle 3-2
(6)
(Byte Enable Controlled)
t
WC
t
WC
t
SKEW
t
SKEW
t
ASC
Address
CE1
HB,
t
AW
t
BW
2
t
WP
t
DW
t
DH
t
WHZ
4
t
OW
t
WP
t
WHZ
4
t
DH
t
DW
t
OW
WE
Data In
Data Out
t
AHC
t
BW
2
t
WR
3
t
WR
3
t
AS
1
t
AS
1
t
SKEW
Notes: 1. t
AS
is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (t
WP
, t
BW
) of a low
3. t
WR
is measured from the earliest of
4. OE level is high or low.
5. Transition is measured
±
500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high for Write Cycle.
1
CE
, WE and (HB and, or LB ).
CE
or WE or (HB and, or LB ) going high to the end of the Write cycle.
1
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