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參數(shù)資料
| 型號： | A6259KLW |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | 8-BIT ADDRESSABLE DMOS POWER DRIVER |
| 中文描述： | 8位可尋址的DMOS功率驅(qū)動器 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 172K |
| 代理商： | A6259KLW |
6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
www.allegromicro.com
TERMINAL DESCRIPTIONS
Terminal No.
1
Terminal Name
POWER GROUND
Function
Reference terminal for output voltage measurements (OUT
0-3
).
(V
DD
) The logic supply voltage (typically 5 V).
Binary-coded output-select input, least-significant bit.
Current-sinking, open-drain DMOS output, address 000.
Current-sinking, open-drain DMOS output, address 001.
Current-sinking, open-drain DMOS output, address 010.
Current-sinking, open-drain DMOS output, address 011.
Binary-coded output-select input.
Reference terminal for input voltage measurements.
Reference terminal for output voltage measurements (OUT
0-3
).
Reference terminal for output voltage measurements (OUT
4-7
).
Binary-coded output-select input, most-significant bit.
Mode control input; see Function Table.
Current-sinking, open-drain DMOS output, address 100.
Current-sinking, open-drain DMOS output, address 101.
Current-sinking, open-drain DMOS output, address 110.
Current-sinking, open-drain DMOS output, address 111.
CMOS data input to the addressed output latch. When enabled, the
addressed output inverts the data input (DATA = HIGH, OUTPUT = LOW).
Mode control input; see Function Table.
Reference terminal for output voltage measurements (OUT
4-7
).
2
3
4
5
6
7
8
9
LOGIC SUPPLY
S
0
OUT
0
OUT
1
OUT
2
OUT
3
S
1
LOGIC GROUND
POWER GROUND
POWER GROUND
S
2
ENABLE
OUT
4
OUT
5
OUT
6
OUT
7
DATA
10
11
12
13
14
15
16
17
18
19
20
CLEAR
POWER GROUND
NOTE — Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point.
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