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參數(shù)資料
| 型號(hào)： | A6259KLW |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | 8-BIT ADDRESSABLE DMOS POWER DRIVER |
| 中文描述： | 8位可尋址的DMOS功率驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大小： | 172K |
| 代理商： | A6259KLW |
D
2
8-BIT ADDRESSABLE
DMOS POWER DRIVER
The A6259KA and A6259KLW combine a 3-to-8 line CMOS
decoder and accompanying data latches, control circuitry, and DMOS
outputs in a multi-functional power driver capable of storing single-line
data in the addressable latches or use as a decoder or demuliplexer.
Driver applications include relays, solenoids, and other medium-current
or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with micro-
processor-based systems. Use with TTL may require appropriate pull-
up resistors to ensure an input logic high. Four modes of operation are
selectable with the CLEAR and ENABLE inputs.
The addressed DMOS output inverts the DATA input with all
unaddressed outputs remaining in their previous states. All of the output
drivers are disabled (the DMOS sink drivers turned off) with the
CLEAR input low and the ENABLE input high. The A6259KA/KLW
DMOS open-drain outputs are capable of sinking up to 750 mA. Similar
devices with reduced r
DS(on)
are available as the A6A259.
The A6259KA is furnished in a 20-pin dual in-line plastic package.
The A6259KLW is furnished in a 20-lead wide-body, small-outline
plastic package (SOIC) with gull-wing leads for surface-mount applica-
tions. Copper lead frames, reduced supply current requirements, and
low on-state resistance allow both devices to sink 150 mA from all
outputs continuously, to ambient temperatures over 85
°
C.
FEATURES
I
50 V Minimum Output Clamp Voltage
I
250 mA Output Current (all outputs simultaneously)
I
1.3
Typical
r
DS(on)
I
Low Power Consumption
I
Replacements for TPIC6259N and TPIC6259DW
6259
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
Note that the A6259KA (DIP) and the A6259KLW
(SOIC) are electrically identical and share a
common terminal number assignment.
LOGIC
GROUND
1
2
3
8
9
13
14
15
16
17
19
4
5
6
7
12
18
20
DATA
S (LSB)
LOGIC
SUPPLY
V
DD
POWER
GROUND
CLEAR
OUT
7
OUT
6
OUT
5
Dwg. PP-050-2
OUT
0
OUT
1
OUT
2
OUT
3
OUT
4
10
11
POWER
GROUND
POWER
GROUND
ENABLE
EN
POWER
GROUND
L
D
L
S
1
S (MSB)
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25
°
C
Output Voltage, V
O
............................
50 V
Output Drain Current,
Continuous, I
O
......................
250 mA
*
Peak, I
OM
.............................
750 mA*
Peak, I
OM
...................................
2.0 A
Single-Pulse Avalanche Energy,
E
AS
.............................................
75 mJ
Logic Supply Voltage, V
DD
..............
7.0 V
Input Voltage Range,
V
I
...............................
-0.3 V to +7.0 V
Package Power Dissipation,
P
D
.......................................
See Graph
Operating Temperature Range,
T
A
.............................
-40
°
C to +125
°
C
Storage Temperature Range,
T
S
.............................
-55
°
C to +150
°
C
*Each output, all outputs on.
Pulse duration
≤
100
μ
s, duty cycle
≤
2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to
damage if exposed to extremely high static
electrical charges.
Always order by complete part number:
Part Number
A6259KA
A6259KLW
Package
20-pin DIP
20-lead SOIC
R
θ
JA
55
°
C/W
70
°
C/W
R
θ
JC
25
°
C/W
17
°
C/W
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