Revision 11 2-27 Table 2-35 3.3 V LVCMOS Wide Range High Slew Commercial-Case Conditions: T
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A3PN250-1VQG100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 51/114闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA NANO 250K GATES 100-VQFP
妯欐簴鍖呰锛� 90
绯诲垪锛� ProASIC3 nano
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 68
闁€鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-TQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�鐣跺墠绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�
ProASIC3 nano Flash FPGAs
Revision 11
2-27
Table 2-35 3.3 V LVCMOS Wide Range High Slew
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250
Drive
Strength
Equivalent
Software
Default
Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tPYS tEOUT
tZL
tZH
tLZ
tHZ
Units
100 A
2 mA
Std.
0.60
10.83 0.04
1.57 2.18
0.43
10.83 9.48
3.25
3.56
ns
鈥�1
0.51
9.22
0.04
1.33 1.85
0.36
9.22
8.06
2.77
3.03
ns
鈥�2
0.45
8.09
0.03
1.17 1.62
0.32
8.09
7.08
2.43
2.66
ns
100 A
4 mA
Std.
0.60
10.83 0.04
1.57 2.18
0.43
10.83 9.48
3.25
3.56
ns
鈥�1
0.51
9.22
0.04
1.33 1.85
0.36
9.22
8.06
2.77
3.03
ns
鈥�2
0.45
8.09
0.03
1.17 1.62
0.32
8.09
7.08
2.43
2.66
ns
100 A
6 mA
Std.
0.60
6.78
0.04
1.57 2.18
0.43
6.78
5.72
3.72
4.35
ns
鈥�1
0.51
5.77
0.04
1.33 1.85
0.36
5.77
4.87
3.16
3.70
ns
鈥�2
0.45
5.06
0.03
1.17 1.62
0.32
5.06
4.27
2.78
3.25
ns
100 A
8 mA
Std.
0.60
6.78
0.04
1.57 2.18
0.43
6.78
5.72
3.72
4.35
ns
鈥�1
0.51
5.77
0.04
1.33 1.85
0.36
5.77
4.87
3.16
3.70
ns
鈥�2
0.45
5.06
0.03
1.17 1.62
0.32
5.06
4.27
2.78
3.25
ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
3. Software default selection highlighted in gray.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
A3PN250-Z1VQG100I IC FPGA NANO 250K GATES 100-VQFP
HMM43DRYS CONN EDGECARD 86POS DIP .156 SLD
HSM36DRAS CONN EDGECARD 72POS R/A .156 SLD
HMM36DRAS CONN EDGECARD 72POS R/A .156 SLD
HMC35DRYS-S93 CONN EDGECARD 70POS DIP .100 SLD
鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁�(sh霉)
鍙冩暩(sh霉)鎻忚堪
A3PN250-2QNG100 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA PROASIC3 NANO 250K GATES COMM 130NM 1.5V 100QFN - Trays 鍒堕€犲晢:Microsemi SOC Products Group 鍔熻兘鎻忚堪:FPGA PROASIC3 NANO 250K GATES COMM 130NM 1.5V 100QFN - Trays
A3PN250-2QNG100I 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA PROASIC3 NANO FAMILY 250K GATES 130NM (CMOS) TECHNOLOG - Trays 鍒堕€犲晢:Microsemi SOC Products Group 鍔熻兘鎻忚堪:FPGA PROASIC3 NANO FAMILY 250K GATES 130NM (CMOS) TECHNOLOG - Trays
A3PN250-2VQ100 鍔熻兘鎻忚堪:IC FPGA NANO 250K GATES 100-VQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 nano 妯欐簴鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:289-CSP锛�14x14锛�
A3PN250-2VQ100I 鍔熻兘鎻忚堪:IC FPGA NANO 250K GATES 100-VQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 nano 妯欐簴鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:289-CSP锛�14x14锛�
A3PN250-2VQG100 鍔熻兘鎻忚堪:IC FPGA NANO 250K GATES 100-VQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 nano 妯欐簴鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:289-CSP锛�14x14锛�