2-12 Revision 11 User I/O Characteristics Timing Model Figure 2-2 Timing Model
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A3PN250-1VQG100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 34/114闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA NANO 250K GATES 100-VQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� ProASIC3 nano
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 68
闁€(m茅n)鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)鐣�(d膩ng)鍓嶇34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)绗�42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)绗�45闋�(y猫)绗�46闋�(y猫)绗�47闋�(y猫)绗�48闋�(y猫)绗�49闋�(y猫)绗�50闋�(y猫)绗�51闋�(y猫)绗�52闋�(y猫)绗�53闋�(y猫)绗�54闋�(y猫)绗�55闋�(y猫)绗�56闋�(y猫)绗�57闋�(y猫)绗�58闋�(y猫)绗�59闋�(y猫)绗�60闋�(y猫)绗�61闋�(y猫)绗�62闋�(y猫)绗�63闋�(y猫)绗�64闋�(y猫)绗�65闋�(y猫)绗�66闋�(y猫)绗�67闋�(y猫)绗�68闋�(y猫)绗�69闋�(y猫)绗�70闋�(y猫)绗�71闋�(y猫)绗�72闋�(y猫)绗�73闋�(y猫)绗�74闋�(y猫)绗�75闋�(y猫)绗�76闋�(y猫)绗�77闋�(y猫)绗�78闋�(y猫)绗�79闋�(y猫)绗�80闋�(y猫)绗�81闋�(y猫)绗�82闋�(y猫)绗�83闋�(y猫)绗�84闋�(y猫)绗�85闋�(y猫)绗�86闋�(y猫)绗�87闋�(y猫)绗�88闋�(y猫)绗�89闋�(y猫)绗�90闋�(y猫)绗�91闋�(y猫)绗�92闋�(y猫)绗�93闋�(y猫)绗�94闋�(y猫)绗�95闋�(y猫)绗�96闋�(y猫)绗�97闋�(y猫)绗�98闋�(y猫)绗�99闋�(y猫)绗�100闋�(y猫)绗�101闋�(y猫)绗�102闋�(y猫)绗�103闋�(y猫)绗�104闋�(y猫)绗�105闋�(y猫)绗�106闋�(y猫)绗�107闋�(y猫)绗�108闋�(y猫)绗�109闋�(y猫)绗�110闋�(y猫)绗�111闋�(y猫)绗�112闋�(y猫)绗�113闋�(y猫)绗�114闋�(y猫)
ProASIC3 nano DC and Switching Characteristics
2-12
Revision 11
User I/O Characteristics
Timing Model
Figure 2-2 Timing Model
Operating Conditions: 鈥�2 Speed, Commercial Temperature Range (TJ = 70掳C), Worst Case
VCC = 1.425 V, with Default Loading at 10 pF
DQ
Y
DQ
Y
Combinational Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
Register Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
LVCMOS 2.5V Output Drive
Strength = 8 mA High Slew Rate
Input LVCMOS 2.5 V
LVCMOS 1.5 V
LVTTL 3.3 V Output drive
strength = 8 mA High slew rate
Y
Combinational Cell
Y
Combinational Cell
Y
Combinational Cell
I/O Module
(Non-Registered)
LVTTLOutput drive strength = 8 mA
High slew rate
I/O Module
(Non-Registered)
LVCMOS 1.5 VOutput drive strength = 2 mA
High slew rate
LVTTLOutput drive strength = 4 mA
High slew rate
I/O Module
(Non-Registered)
Input LVTTL
Clock
Input LVTTL
Clock
Input LVTTL
Clock
tPD = 0.56 ns
tPD = 0.49 ns
tDP = 2.25 ns
tPD = 0.87 ns
tDP = 2.87 ns
tPD = 0.51 ns
tDP = 2.21 ns
tPD = 0.47 ns
tDP = 3.02 ns
tPD = 0.47 ns
tPY = 0.84 ns
tCLKQ = 0.55 ns
tOCLKQ = 0.59 ns
tSUD = 0.43 ns
tOSUD = 0.31 ns
tDP = 2.21 ns
tPY = 0.84 ns
tPY = 1.14 ns
tCLKQ = 0.55 ns
tSUD = 0.43 ns
tPY = 0.84 ns
tICLKQ = 0.24 ns
tISUD = 0.26 ns
tPY = 1.04 ns
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A3PN250-Z1VQG100I IC FPGA NANO 250K GATES 100-VQFP
HMM43DRYS CONN EDGECARD 86POS DIP .156 SLD
HSM36DRAS CONN EDGECARD 72POS R/A .156 SLD
HMM36DRAS CONN EDGECARD 72POS R/A .156 SLD
HMC35DRYS-S93 CONN EDGECARD 70POS DIP .100 SLD
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鍙冩暩(sh霉)鎻忚堪
A3PN250-2QNG100 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA PROASIC3 NANO 250K GATES COMM 130NM 1.5V 100QFN - Trays 鍒堕€犲晢:Microsemi SOC Products Group 鍔熻兘鎻忚堪:FPGA PROASIC3 NANO 250K GATES COMM 130NM 1.5V 100QFN - Trays
A3PN250-2QNG100I 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA PROASIC3 NANO FAMILY 250K GATES 130NM (CMOS) TECHNOLOG - Trays 鍒堕€犲晢:Microsemi SOC Products Group 鍔熻兘鎻忚堪:FPGA PROASIC3 NANO FAMILY 250K GATES 130NM (CMOS) TECHNOLOG - Trays
A3PN250-2VQ100 鍔熻兘鎻忚堪:IC FPGA NANO 250K GATES 100-VQFP RoHS:鍚� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪锛� 绯诲垪:ProASIC3 nano 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€(m茅n)鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
A3PN250-2VQ100I 鍔熻兘鎻忚堪:IC FPGA NANO 250K GATES 100-VQFP RoHS:鍚� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪锛� 绯诲垪:ProASIC3 nano 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€(m茅n)鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
A3PN250-2VQG100 鍔熻兘鎻忚堪:IC FPGA NANO 250K GATES 100-VQFP RoHS:鏄� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪锛� 绯诲垪:ProASIC3 nano 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€(m茅n)鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
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