參數(shù)資料
型號: A3PE1500-PQG208I
元件分類: FPGA
英文描述: FPGA, 38400 CLBS, 1500000 GATES, PQFP208
封裝: 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù): 128/152頁
文件大?。?/td> 4932K
代理商: A3PE1500-PQG208I
ProASIC3E DC and Switching Characteristics
v1.2
2 - 65
Global Resource Characteristics
A3PE600 Clock Tree Topology
Clock delays are device-specific. Figure 2-37 is an example of a global tree used for clock routing.
The global tree presented in Figure 2-37 is driven by a CCC located on the west side of the A3PE600
device. It is used to drive all D-flip-flops in the device.
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be
driven and conditioned internally by the CCC module. For more details on clock conditioning
global clock delays within the device. Minimum and maximum delays are measured with minimum
and maximum loading.
Figure 2-37 Example of Global Tree Use in an A3PE600 Device for Clock Routing
Central
Global Rib
VersaTile
Rows
Global Spine
CCC
相關PDF資料
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A3PE1500-PQG208 FPGA, 38400 CLBS, 1500000 GATES, PQFP208
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