參數(shù)資料
型號： A3PE1500-PQG208I
元件分類： FPGA
英文描述： FPGA, 38400 CLBS, 1500000 GATES, PQFP208
封裝： 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù)： 110/152頁
文件大?。?/td> 4932K
代理商： A3PE1500-PQG208I
ProASIC3E DC and Switching Characteristics
2- 48
v1.2
Timing Characteristics
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard
to high-performance multipoint bus applications. Multidrop and multipoint bus configurations
may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the
higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers
require series terminations for better signal quality and to control voltage swing. Termination is
also required at both ends of the bus since the driver can be located anywhere on the bus. These
configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with
appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz
with a maximum of 20 loads. A sample application is given in Figure 2-22. The input and output
buffer delays are available in the LVDS section in Table 2-76.
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the
required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver:
RS =60 Ω and RT =70 Ω, given Z0 =50 Ω (2") and Zstub =50 Ω (~1.5").
Table 2-76 LVDS
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Speed Grade
tDOUT
tDP
tDIN
tPY
Units
–F
0.79
2.25
0.05
2.18
ns
Std.
0.66
1.87
0.04
1.82
ns
–1
0.56
1.59
0.04
1.55
ns
–2
0.49
1.40
0.03
1.36
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating
values.
Figure 2-22 B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
...
R
T
R
T
BIBUF_LVDS
R
+
-
T
+
-
R
+
-
T
+
-
D
+
-
EN
Receiver
Transceiver
Receiver
Transceiver
Driver
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
Z
stub
Z
stub
Z
stub
Z
stub
Z
stub
Z
stub
Z
stub
Z
stub
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
相關(guān)PDF資料
PDF描述
A3PE1500-PQG208 FPGA, 38400 CLBS, 1500000 GATES, PQFP208
A3PN060-FVQ100 FPGA, 1536 CLBS, 60000 GATES, PQFP100
A3PN060-FVQG100 FPGA, 1536 CLBS, 60000 GATES, PQFP100
A3PN060-ZFVQ100 FPGA, 1536 CLBS, 60000 GATES, PQFP100
A3PN060-ZFVQG100 FPGA, 1536 CLBS, 60000 GATES, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3PE1500-PQG896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE1500-PQG896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE1500-PQG896I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE1500-PQG896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE3000-1FG324 功能描述:IC FPGA 1KB FLASH 3M 324-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3E 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*