參數(shù)資料
型號: A3PE1500-PQG208
元件分類: FPGA
英文描述: FPGA, 38400 CLBS, 1500000 GATES, PQFP208
封裝: 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù): 79/152頁
文件大?。?/td> 4932K
代理商: A3PE1500-PQG208
ProASIC3E DC and Switching Characteristics
2- 20
v1.2
Detailed I/O DC Characteristics
Table 2-18 Input Capacitance
Symbol
Definition
Conditions
Min.
Max.
Units
CIN
Input capacitance
VIN = 0, f = 1.0 MHz
8
pF
CINCLK
Input capacitance on the clock pin
VIN = 0, f = 1.0 MHz
8
pF
Table 2-19 I/O Output Buffer Maximum Resistances1
Standard
Drive Strength
RPULL-DOWN (Ω)
2
RPULL-UP (Ω)
3
3.3 V LVTTL / 3.3 V LVCMOS
4 mA
100
300
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
2.5 V LVCMOS
4 mA
100
200
8 mA
50
100
12 mA
25
50
16 mA
20
40
24 mA
11
22
1.8 V LVCMOS
2 mA
200
225
4 mA
100
112
6 mA
50
56
8 mA
50
56
12 mA
20
22
16 mA
20
22
1.5 V LVCMOS
2 mA
200
224
4 mA
100
112
6 mA
67
75
8 mA
33
37
12 mA
33
37
3.3 V PCI/PCI-X
Per PCI/PCI-X specification
25
75
3.3 V GTL
25 mA
11
2.5 V GTL
25 mA
14
3.3 V GTL+
35 mA
12
2.5 V GTL+
33 mA
15
HSTL (I)
8 mA
50
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer
resistance values depend on VCCI, drive strength selection, temperature, and process. For
board design considerations and detailed output buffer resistances, use the corresponding
IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
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