參數(shù)資料
型號: A3PE1500-PQG208
元件分類: FPGA
英文描述: FPGA, 38400 CLBS, 1500000 GATES, PQFP208
封裝: 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù): 70/152頁
文件大?。?/td> 4932K
代理商: A3PE1500-PQG208
ProASIC3E DC and Switching Characteristics
2- 12
v1.2
User I/O Characteristics
Timing Model
Figure 2-2 Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case
VCC = 1.425 V
DQ
Y
DQ
Y
Combinational Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
Register Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
LVPECL
LVDS,
BLVDS,
M-LVDS
GTL+ 3.3V
Y
Combinational Cell
Y
Combinational Cell
Y
Combinational Cell
I/O Module
(Non-Registered)
LVTTL/LVCMOS
Output drive strength = 24 mA
High slew rate
I/O Module
(Non-Registered)
LVCMOS 1.5V
Output drive strength = 12 mA
High slew
LVTTL/LVCMOS
Output drive strength = 12 mA
High slew rate
I/O Module
(Non-Registered)
Input LVTTL/LVCMOS
Clock
Input LVTTL/LVCMOS
Clock
Input LVTTL/LVCMOS
Clock
t
PD = 0.56 ns
t
PD = 0.49 ns
t
DP = 1.36 ns
t
PD = 0.87 ns
t
DP = 2.74 ns
t
PD = 0.51 ns
t
PD = 0.47 ns
t
DP = 2.39 ns
t
DP = 3.30 ns
t
CLKQ = 0.59 ns
t
DP = 1.53 ns
t
SUD = 0.31 ns
t
PY = 0.90 ns
t
CLKQ = 0.55 ns
t
SUD = 0.43 ns
t
PY = 0.90 ns
t
PD = 0.47 ns
t
CLKQ = 0.55 ns
t
SUD = 0.43 ns
t
PY = 1.36 ns
t
PY = 0.90 ns
t
ICLKQ = 0.24 ns
t
ISUD = 0.26 ns
t
PY = 1.22 ns
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