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參數(shù)資料
| 型號： | A3251LUA-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 300K |
| 描述： | IC SW HALL EFFECT UNI 3-SIP |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 傳感范圍： | 50G |
| 類型： | 單極開關(guān) |
| 電源電壓： | 4.2 V ~ 24 V |
| 電流 - 電源： | 10mA |
| 電流 - 輸出（最大）： | 20mA |
| 輸出類型： | 數(shù)字，開路集電極 |
| 特點(diǎn)： | 穩(wěn)壓電壓 |
| 工作溫度： | -40°C ~ 150°C |
| 封裝/外殼： | 3-SIP |
| 供應(yīng)商設(shè)備封裝： | 3-SIP |
| 包裝： | 散裝 |
Field-Programmable, Chopper-Stabilized,
Unipolar Hall-Effect Switches
A3250 and
A3251
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
V
PH
V+
t
V
PM
V
PL
0
Address 1
Address 2
Address n ( d 63)
Figure 5. Pulse sequence to select addresses
Falling edge of final B
OP
address digit
V
PH
V+
t
V
PM
V
PL
0
Encode Lock Bit
Enable
Address
Blow
7 pulses
65 pulses
Figure 6. Pulse sequence to encode lock bit
Lock Bit Programming. After the desired B
OP
calibration value
is programmed, and all of the corresponding bitfield-level fuses
are blown, the device-level fuse should be blown. To do so, the
lock bit (bitfield address 65) should be encoded as 1 and have
its fuse blown. This is done in the same manner as permanently
setting the other bitfields, as shown in figure 6.
Address Selection. After addressing mode is enabled, the
target bitfield address, is indicated by a series of VPM pulses,
as shown in figure 3. When provisionally trying a value, this
sequence is followed by a short V
PH
pulse, which serves to
delimit the address and set the corresponding bitfield. When
permanently setting a bitfield, the V
PH
pulse is continued for a
longer period of time, suffienct to not only set the bitfield to 1,
but also to blow the bitfield fuse.
Enabling Addressing Mode. The first segment of code is a
keying sequence used to enable the bitfield addressing mode. As
shown in figure 4, this segment consists of one short V
PH
pulse,
seven or more V
PM
pulses, and one short V
PH
pulse, with no
supply interruptions. This sequence is designed to prevent the
device from being programmed accidentally, such as by noise on
the supply line.
V
PH
V+
t
V
PM
V
PL
0
Minimum 7 pulses
Figure 4. Addressing mode enable pulse sequence
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A3251LUATL | 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:Field-Programmable, Chopper-Stabilized Unipolar Hall-Effect Switches |
| A325400284-200 | 制造商: 功能描述: 制造商:undefined 功能描述: |
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