參數(shù)資料
型號(hào)： A1400AMT3C
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA453
封裝： STAGGERED, CERAMIC, PGA-453
文件頁(yè)數(shù)： 18/90頁(yè)
文件大小： 1497K
代理商： A1400AMT3C
Chapter 4
Power Management
11
23792I—June 2001
AMD Athlon Processor Model 4 Data Sheet
Preliminary Information
The Stop Grant state is also entered for the S1 system sleep
state based on a write to the SLP_TYP field in the ACPI-defined
power management 1 control register. During the S1 sleep
state, system software ensures no bus master or probe activity
occurs.
After recognizing the assertion of STPCLK#, the AMD Athlon
Processor Model 4 completes all pending and in-progress bus
cycles and acknowledges the STPCLK# assertion by issuing a
Stop Grant special bus cycle to the AMD Athlon system bus.
After the Northbridge disconnects the AMD Athlon system bus
in response to the Stop Grant special bus cycle, the processor
enters a low-power state dictated by the CLK_Ctl register.
During the Stop Grant states, the processor latches INIT#,
INTR, NMI, and SMI#, or a local APIC interrupt message if they
are asserted.
The Stop Grant state is exited upon the deassertion of
STPCLK# or the assertion of RESET#. When STPCLK# is
deasserted, the processor initiates a connection of the
AMD Athlon system bus if it is disconnected. After the
processor enters the Working state, any pending interrupts are
recognized and serviced and the processor resumes execution
at the instruction boundary where STPCLK# was initially
recognized.
If RESET# is sampled asserted during the Stop Grant state, the
processor returns to the Working state and the reset process
begins.
Probe State
The Probe state is entered when the Northbridge initiates an
AMD Athlon system bus connect as required to probe the
processor. If the processor has been disconnected from the
system bus, the Northbridge must initiate a system bus
connection prior to probing the processor to snoop the
processor’s caches for example. When in the Probe state, the
processor responds to a probe cycle in the same manner as
when it is in the Working state.
When the probe has been serviced, the processor returns to the
same state as when it entered the Probe state (Halt or Stop
Grant state). Once in the Halt or Stop Grant state, a low-power
s t ate i s only achieve d i f the N o rthbri d ge ini t ia tes a
disconnection from the system bus.
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