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參數(shù)資料
| 型號： | A1356LKB-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 432K |
| 描述： | IC SENSOR HALL EFFECT 3 SIP |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 傳感范圍： | 45m%D/G ~ 75m%D/G |
| 類型： | 線性 - 可編程 |
| 電源電壓： | 4.5 V ~ 18 V |
| 電流 - 電源： | 10mA |
| 電流 - 輸出（最大）： | 25mA |
| 輸出類型： | 數(shù)字式， PWM 編碼 |
| 特點(diǎn)： | 高精度 |
| 工作溫度： | -40°C ~ 150°C |
| 封裝/外殼： | 3-SIP |
| 供應(yīng)商設(shè)備封裝： | 3-SIP |
| 包裝： | 散裝 |
| 其它名稱： | 620-1369 A1356LK-T |
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
13
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Mode and Parameter Selection
Each programmable mode and parameter can be accessed through
specific registers. To select a register, a sequence of voltage
pulses consisting of a V
P(HIGH)
pulse, a series of V
P(MID)
pulses,
and a V
P(HIGH)
pulse (with no VCC supply interruptions) must be
applied serially to the supply pin. The quantity of V
P(MID)
pulses
is called the key, and uniquely identifies each register. The pulse
train used for selection of the first register, key 1, is shown in
figure 4.
The A1356 has two registers that select among the three program-
mable modes:
" Register Mode 1:
Blow and Lock modes
" Register Mode 2:
Try mode
And there are four registers that select among the four program-
mable parameters:
" Register 1:
Sensitivity, Sens
" Register 2:
Quiescent duty cycle output, D
(Q)
" Register 3:
Pulse width modulated carrier frequency , f
PWM
" Register 5:
Lock (device locking)
Bit Field Addressing
After a programmable parameter has been selected, a V
P(HIGH)
pulse transitions the programming logic into the bit field address-
ing state. Applying a series of V
P(MID)
pulses to the VCC pin of
the device, as shown in figure 5, increments the bit field of the
selected parameter.
When addressing the bit field, the number of V
P(MID)
pulses
is represented by a decimal number called a code. Addressing
activates the corresponding fuse locations in the given bit field
by increasing the binary value of an internal DAC. The value of
the bit field (and code) increases by one with the falling edge
of each V
P(MID)
pulse, up to the maximum possible code (see
the Programming Logic table). As the value of the bit field code
increases, the value of the programmable parameter changes.
Measurements can be taken after each pulse to determine if the
required result for the programmable parameter has been reached.
Cycling the supply voltage resets all the locations in the bit field
that have unblown fuses to their initial states.
Fuse Blowing
After the required code is found for a given parameter, its value
can be set permanently by blowing individual fuses in the appro-
priate register bit field. Blowing is accomplished by applying a
V
P(HIGH)
pulse, called a blow pulse, of sufficient duration at the
V
P(HIGH)
level to permanently set an addressed bit by blowing a
fuse internal to the device. Due to power requirements, the fuse
for each bit in the bit field must be blown individually. To accom-
plish this, the code representing the required parameter value
must be translated to a binary number. For example, as shown
in figure 6, decimal code 5 is equivalent to the binary number
101. Therefore bit 2 (code 4) must be addressed and blown, the
device power supply cycled, and then bit 0 (code 1) addressed
Programming Procedures
Figure 4. Parameter selection pulse train. This shows the sequence for
selecting the register corresponding to key 1, indicated by a single V
P(MID)
pulse.
V+
0
t
LOW
t
ACTIVE
V
P(HIGH)
V
P(MID)
V
P(LOW)
Figure 5. Bit field addressing pulse train. Addressing the bit field by
increasing the code causes the programmable parameter value to change.
The number of bits available for a given programming code, n, varies
among parameters; for example, the bit field for D
(Q)
has 8 bits available,
which allows 255 separate codes to be used.
V+
0
V
P(HIGH)
V
P(MID)
V
P(LOW)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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