Notes: 1. All dimensions are in inches unless otherwise " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A1010B-1VQ80I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 88/98闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1200 GATES 80-VQFP IND
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� ACT™ 1
LAB/CLB鏁�(sh霉)锛� 295
杓稿叆/杓稿嚭鏁�(sh霉)锛� 57
闁€鏁�(sh霉)锛� 1200
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 80-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 80-VQFP锛�14x14锛�
89
Hi R e l F P GA s
P ack ag e Mec h a n i c a l Dr awi n gs
84- Pi n CP GA
Notes:
1.
All dimensions are in inches unless otherwise stated.
2.
BSC鈥擝asic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
Orientation Pin
1.100"
卤 .020" square
.080"
.110"
.120"
.140"
.100" BSC
0.18"
卤 .002"
.050"
卤 .010"
1.000 BSC
.045
.055
L
K
J
H
G
F
E
D
C
B
A
11
10
9
8
7
6
5
4
3
2
1
Pin #1 ID
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
CAT93C86VI-G IC EEPROM 16KBIT 3MHZ 8SOIC
993-009-020R121 BACKSHELL DB9 45DEG MET PLASTIC
CAT24C128YI-GT3 IC EEPROM 128KBIT 400KHZ 8TSSOP
A1020B-VQG80C IC FPGA 2K GATES 80-VQFP COM
977-050-010R031 BACKSHELL DB50 PLAIN PLASTIC
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A1010B-1VQ84B 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs
A1010B-1VQ84C 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs
A1010B-1VQ84I 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs
A1010B-1VQ84M 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs
A1010B-1VQG80C 鍔熻兘鎻忚堪:IC FPGA 1200 GATES 80-VQFP COM RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ACT™ 1 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�