(W or s t - C as e M i l i t a r y Cond i t i o n s , V <" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A1010B-1VQ80I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 20/98闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1200 GATES 80-VQFP IND
妯欐簴鍖呰锛� 90
绯诲垪锛� ACT™ 1
LAB/CLB鏁�(sh霉)锛� 295
杓稿叆/杓稿嚭鏁�(sh霉)锛� 57
闁€鏁�(sh霉)锛� 1200
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 80-TQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 80-VQFP锛�14x14锛�
27
Hi R e l F P GA s
A1 24 0A T i m i n g C har a c t e r i st i c s
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25掳C)
鈥樷€�1鈥� Speed
鈥楽td鈥� Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD1
Single Module
5.2
6.1
ns
tCO
Sequential Clk to Q
5.2
6.1
ns
tGO
Latch G to Q
5.2
6.1
ns
tRS
Flip-Flop (Latch) Reset to Q
5.2
6.1
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.9
2.2
ns
tRD2
FO=2 Routing Delay
2.4
2.8
ns
tRD3
FO=3 Routing Delay
3.1
3.7
ns
tRD4
FO=4 Routing Delay
4.3
5.0
ns
tRD8
FO=8 Routing Delay
6.6
7.7
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Setup
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
1.3
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
7.4
8.1
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
7.4
8.1
ns
tA
Flip-Flop Clock Input Period
14.8
18.6
ns
tINH
Input Buffer Latch Hold
2.5
ns
tINSU
Input Buffer Latch Setup
鈥�3.5
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Setup
0.5
ns
fMAX
Flip-Flop (Latch) Clock Frequency
63
54
MHz
Notes:
1.
For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
3.
Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the DirectTime Analyzer utility.
4.
Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
CAT93C86VI-G IC EEPROM 16KBIT 3MHZ 8SOIC
993-009-020R121 BACKSHELL DB9 45DEG MET PLASTIC
CAT24C128YI-GT3 IC EEPROM 128KBIT 400KHZ 8TSSOP
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鍙冩暩(sh霉)鎻忚堪
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