28
A1 24 0A T i m i n g C har a c t e r i st i c s (continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25掳C)
鈥樷€�1鈥� Speed
鈥楽td鈥� Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad to Y High
4.0
4.7
ns
tINYL
Pad to Y Low
3.6
4.3
ns
tINGH
G to Y High
6.9
8.1
ns
tINGL
G to Y Low
6.6
7.7
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
5.8
6.9
ns
tIRD2
FO=2 Routing Delay
6.7
7.8
ns
tIRD3
FO=3 Routing Delay
7.5
8.8
ns
tIRD4
FO=4 Routing Delay
8.2
9.7
ns
tIRD8
FO=8 Routing Delay
10.9
12.9
ns
Global Clock Network
tCKH
Input Low to High
FO = 32
FO = 256
13.3
16.3
15.7
19.2
ns
tCKL
Input High to Low
FO = 32
FO = 256
13.3
16.5
15.7
19.5
ns
tPWH
Minimum Pulse Width High
FO = 32
FO = 256
5.7
6.0
6.7
7.1
ns
tPWL
Minimum Pulse Width Low
FO = 32
FO = 256
5.7
6.0
6.7
7.1
ns
tCKSW
Maximum Skew
FO = 32
FO = 256
0.6
3.1
0.6
3.1
ns
tSUEXT
Input Latch External Setup
FO = 32
FO = 256
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 256
8.6
13.8
8.6
13.8
ns
tP
Minimum Period
FO = 32
FO = 256
11.5
12.2
13.5
14.3
ns
fMAX
Maximum Frequency
FO = 32
FO = 256
87
82
74
70
MHz
Note:
1.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce
delays by 0 to 4 ns.