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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | A1010B-1VQ80C |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 32/98闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA 1200 GATES 80-VQFP COM |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | ACT™ 1 |
| LAB/CLB鏁�(sh霉)锛� | 295 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 57 |
| 闁€鏁�(sh霉)锛� | 1200 |
| 闆绘簮闆诲锛� | 4.5 V ~ 5.5 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 80-TQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 80-VQFP锛�14x14锛� |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�鐣�(d膩ng)鍓嶇32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�
38
A1 42 5A T i m i n g C har a c t e r i st i c s (continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25掳C)
鈥樷€�1鈥� Speed
鈥楽td鈥� Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
CMOS Output Module Timing1
tDHS
Data to Pad, High Slew
9.2
10.8
ns
tDLS
Data to Pad, Low Slew
17.3
20.3
ns
tENZHS
Enable to Pad, Z to H/L, High Slew
7.7
9.1
ns
tENZLS
Enable to Pad, Z to H/L, Low Slew
13.1
15.5
ns
tENHSZ
Enable to Pad, H/L to Z, High Slew
9.9
11.6
ns
tENLSZ
Enable to Pad, H/L to Z, Low Slew
10.5
11.6
ns
tCKHS
IOCLK Pad to Pad H/L, High Slew
12.5
13.7
ns
tCKLS
IOCLK Pad to Pad H/L, Low Slew
18.1
20.1
ns
dTLHHS
Delta Low to High, High Slew
0.06
0.07
ns/pF
dTLHLS
Delta Low to High, Low Slew
0.11
0.13
ns/pF
dTHLHS
Delta High to Low, High Slew
0.04
0.05
ns/pF
dTHLLS
Delta High to Low, Low Slew
0.05
0.06
ns/pF
Dedicated (Hard-Wired) I/O Clock Network
tIOCKH
Input Low to High
(Pad to I/O Module Input)
3.0
3.5
ns
tIOPWH
Minimum Pulse Width High
3.9
4.4
ns
tIOPWL
Minimum Pulse Width Low
3.9
4.4
ns
tIOSAPW
Minimum Asynchronous Pulse Width
3.9
4.4
ns
tIOCKSW
Maximum Skew
0.5
ns
tIOP
Minimum Period
7.9
9.3
ns
fIOMAX
Maximum Frequency
125
100
MHz
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input Low to High
(Pad to S-Module Input)
4.6
5.3
ns
tHCKL
Input High to Low
(Pad to S-Module Input)
4.6
5.3
ns
tHPWH
Minimum Pulse Width High
3.9
4.4
ns
tHPWL
Minimum Pulse Width Low
3.9
4.4
ns
tHCKSW
Maximum Skew
0.4
ns
tHP
Minimum Period
7.9
9.3
ns
fHMAX
Maximum Frequency
125
100
MHz
Notes:
1.
Delays based on 35 pF loading.
2.
SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| A1010B-1VQG80C | IC FPGA 1200 GATES 80-VQFP COM |
| 5745175-1 | CONN BACKSHELL DB50 DIE CAST |
| 5745172-1 | CONN BACKSHELL DB15 DIE CAST |
| A1010B-2PQG100C | IC FPGA 1200 GATES 100-PQFP COM |
| 5748677-4 | CONN BACKSHELL DB37 METAL PLATED |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| A1010B-1VQ80I | 鍔熻兘鎻忚堪:IC FPGA 1200 GATES 80-VQFP IND RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:ACT™ 1 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛� |
| A1010B-1VQ84B | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A1010B-1VQ84C | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A1010B-1VQ84I | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A1010B-1VQ84M | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
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