參數(shù)資料
型號(hào)： 9S12E128DGV1
廠商： Motorola, Inc.
英文描述： MC9S12E-Family Device User Guide V01.04
中文描述： MC9S12E -系列設(shè)備的用戶手冊(cè)V01.04
文件頁數(shù)： 98/156頁
文件大小： 3077K
代理商： 9S12E128DGV1
Device User Guide — 9S12E128DGV1/D V01.04
98
6.6 HCS12 Module Mapping Control (MMC) Block Description
Consult the HCS12 MMC Block Guide for information about the Module Mapping Control module.
Section 7 Analog to Digital Converter (ATD) Block
Description
Consult the ATD_10B16C Block Guide for further information about the A/D Converter module.
Note that V04 of the ATD has an external trigger (ETRIG) function which is tied off and not available for
use.
Section 8 Clock Reset Generator (CRG) Block Description
Consult the CRG Block Guide for information about the Clock and Reset Generator module.
8.1 Device-specific information
The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the
CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified
threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the
VREG Block Guide for voltage level specifications. 3F.
8.1.1 XCLKS
The XCLKS input signal is active low (see
2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7
).
Section 9 Digital to Analog Converter (DAC) Block
Description
There are two digital to analog converter modules (DAC0, DAC1). Consult the DAC Block Guide for
information about the DAC Module.
Section 10 Flash EEPROM Block Description
Consult the FTS32K Block Guide for information about the flash module for the MC9S12E32.
Consult the FTS128K1 Block Guide for information about the flash module for the MC9S12E64.
Consult the FTS128K1 Block Guide for information about the flash module for the MC9S12E128.
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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