參數(shù)資料
型號(hào): 9S12E128DGV1
廠商: Motorola, Inc.
英文描述: MC9S12E-Family Device User Guide V01.04
中文描述: MC9S12E -系列設(shè)備的用戶手冊V01.04
文件頁數(shù): 136/156頁
文件大?。?/td> 3077K
代理商: 9S12E128DGV1
Device User Guide — 9S12E128DGV1/D V01.04
136
Figure B-7 SPI Slave Timing (CPHA=1)
In
Table B-9
the timing characteristics for slave mode are listed.
Table B-9 SPI Slave Mode Timing Characteristics
Num
C
Characteristic
Symbol
Unit
Min
Typ
Max
1
/
4
1
P
SCK Frequency
f
sck
t
sck
t
lead
t
lag
t
wsck
t
su
t
hi
DC
f
bus
t
bus
t
bus
t
bus
t
bus
1
P
SCK Period
4
2
D
Enable Lead Time
4
3
D
Enable Lag Time
4
4
D
Clock (SCK) High or Low Time
4
5
D
Data Setup Time (Inputs)
8
ns
6
D
Data Hold Time (Inputs)
8
ns
7
D
Slave Access Time (time to data
active)
t
a
20
ns
8
D
Slave MISO Disable Time
t
dis
22
ns
9
D
Data Valid after SCK Edge
t
vsck
30 + t
bus
1
30 + t
bus
1
NOTES
:
1. t
bus
added due to internal synchronization delay
ns
10
D
Data Valid after SS fall
t
vss
ns
11
D
Data Hold Time (Outputs)
t
ho
t
rfi
t
rfo
20
ns
12
D
Rise and Fall Time Inputs
8
ns
13
D
Rise and Fall Time Outputs
8
ns
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
1
5
6
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT
SLAVE LSB OUT
BIT 6 . . . 1
4
4
9
12
13
11
(CPOL
=
0)
(CPOL
=
1)
SS
(INPUT)
2
12
13
3
NOTE: Not defined!
SLAVE
7
8
see
note
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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