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參數(shù)資料
| 型號： | 9LPRS535BFLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48 |
| 封裝： | 0.300 INCH, MO-118, SSOP-48 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 216K |
| 代理商： | 9LPRS535BFLF |
14
Integrated
Circuit
Systems, Inc.
ICS9LPRS535
Datasheet
1461A—07/28/09
Test Clarification Table
Comments
FSLC/
TEST_SEL
HW PIN
FSLB/
TEST_MOD
E
HW PIN
TEST
ENTRY BIT
B9b3
REF/N or
HI-Z
B9b4
OUTPUT
<2.0V
X
0
NORMAL
>2.0V
0
X
0
HI-Z
>2.0V
0
X
1
REF/N
>2.0V
1
X
0
REF/N
>2.0V
1
X
1
REF/N
<2.0V
X
1
0
HI-Z
<2.0V
X
1
REF/N
B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B9b4: 1= REF/N, Default = 0 (HI-Z)
HW
SW
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V then use TEST_SEL
If power-up w/ V<2.0V then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a real time input
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through B9b3.
If test mode is invoked by B9b3, only B9b4
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
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相關(guān)代理商/技術(shù)參數(shù) |
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| 9LPRS535BFLFT | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9LPRS535BGLF | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9LPRS535BGLFT | 制造商:Integrated Device Technology Inc 功能描述:48-PIN CK505 FOR INTEL SYSTEMS 制造商:Integrated Device Technology Inc 功能描述:48 TSSOP (LEAD FREE) - Tape and Reel |
| 9LPRS535CFLF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:48-pin CK505 for Intel Systems |
| 9LPRS535CFLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:48-pin CK505 for Intel Systems |
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