參數(shù)資料
型號: 9860
廠商: Intel Corp.
英文描述: Advanced 10/100 Repeater with Intergrated Management
中文描述: 高級10/100中繼器與綜合管理
文件頁數(shù): 38/118頁
文件大?。?/td> 1648K
代理商: 9860
LXT9860/9880
Advanced 10/100 Repeater with Integrated Management
38
Datasheet
Document #: 248987
Revision#: 003
Rev Date: 08/07/01
3.6.2
Clock
A stable, external 25 MHz reference clock source (TTL) is required to the CLK25 pin. The
reference clock is used to generate transmit signals and recover receive signals. A crystal-based
clock is recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to
Table 26 on page 67
for a list of recommended oscillators and to
Table 29 on page 75
for clock
timing requirements.
3.6.3
Bias Resistor
The RBIAS input requires a 22.1 k
, 1% resistor connected to ground.
3.6.4
Reset
At power-up, the reset input must be held Low until VCC reaches at least 3.15V. A buffer should be
used to drive reset if there are multiple LXT98x0 devices. The clock must be active.
Software and hardware resets are identical. Refer to
Table 74 on page 108
and
Table 84 on
page 113
for Software Reset details.
3.6.5
PROM
Although not required, an external, auto-incrementing 48-bit PROM can be used for two purposes:
Support the PROM-based address arbitration scheme on the Serial Management Interface (See
PROM Arbitration Mechanism
on page 58
.)
Assign a unique ID and upload configuration data to all LXT98x0s on a board
Multiple devices on the same board can share a single common PROM. The LXT98x0 with
ChipID = 00 actively reads the PROM at power-up; all other LXT98x0s
listen in
. If PROM
arbitration is not used, the PROM data input signal must be tied either High or Low. (See
Serial
PROM Interface
on page 59
.)
3.6.6
Chip ID
Each cascaded LXT98x0 requires a unique 2-bit Chip ID value. The Serial Management Interface
(SMI) identifies each IC by ChipID. One LXT98x0 on each board must be assigned ChipID = 00.
In the Header Field, the Chip Address is defined by three bits. The Most Significant Bit (MSB) = 0;
the value of the other two bits is set by pins. Refer to
Serial Management I/F
on page 52
.
3.6.7
Management Master I/O Link
In multiple device applications, the Management Master daisy chain (MMSTRIN/MMSTROUT)
ensures that collisions are counted correctly. Connect the MMSTRIN input to the MMSTROUT
output of the previous device when cascading and stacking. Ground the MMSTRIN input of the
first or only device. In hot-swap applications, resistive bypassing can be used with a 1 - 3 k
value.
3.6.8
IRB Bus Pull-ups
Even when the LXT98x0 is used in a stand-alone configuration, pull-up resistors are required on
the IRB signals listed. See
Figure 30 on page 74
and
Figure 31 on page 74
for sample circuits.
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