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參數(shù)資料
| 型號： | 9860 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 10/100 Repeater with Intergrated Management |
| 中文描述： | 高級10/100中繼器與綜合管理 |
| 文件頁數(shù)： | 110/118頁 |
| 文件大?。?/td> | 1648K |
| 代理商： | 9860 |
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LXT9860/9880
—
Advanced 10/100 Repeater with Integrated Management
110
Datasheet
Document #: 248987
Revision#: 003
Rev Date: 08/07/01
12
Enable Port
Late Event
Enable Port Late Event
0 = does not allow out of window collisions to increment port
Late Event counters.
1 = does allow out of window collisions to increment port Late
Event counters.
R/W
0
11
Register Clear
Register Clear
0 = clears appropriate registers upon serial read.
1 = requires that appropriate register bits be written to be
cleared. (Write a
‘
1
’
to the bit(s) that are to be cleared.)
R/W
0
10
Statistics Enable
Statistics Enable-Turns statistics gathering on and off.
R/W
1
9
Send /T/R
Send /T/R - Forces a good /T/R after each 100 Mbps
transmission
R/W
0
8
Isolate100
Isolate100 - Isolates the IR100CFS stack signal and provides
an output pin for disabling an external backplane transceiver
R/W
0
7
Isolate10
Isolate10 - Same as for 100 except also isolates stack
IR10COLBP and IR10CFSBP signal.
R/W
0
6
Unicast Frame
count
Unicast Frame count
1 = portReadableFrames count only Unicast Frames.
0 = portReadableFrames count all Frames.
R/W
0
5
Arbitration Value
Arbitration Input Value-as read from input pin
R
0
4
Zero Counters
Zero Counters
1 = LXT98x0 sequentially walks through each counter location
and zero its contents. When all counter locations have been
cleared, this bit is reset to
‘
0
’
.
0 = normal
R/W
0
3
Enable FIFO
error
Enable FIFO error
1 = LXT98x0 enters transmit collision upon detection of a data
rate mismatch.
0 = Normal
R/W
1
2
Reserved
Reserved - Write as
‘
0
’
, ignore on Read.
R/W
0
Table 76. Repeater Serial Configuration
Bit
Name
Description
Type
1
Default
31:8
Reserved
Reserved.
R
0
7:2
RptrSerConfig
Bits 7:2 of Configuration Interface data. (8-bit mode). Refer to
Table
75
, bit 14 description.
R
0
1:0
RptrSerConfig
Bits 1:0 of Configuration Interface data. Refer to
Table 75,
bit 14
description.
R
0
1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing
Table 75. Repeater Configuration Register (Continued)
Bit
Name
Description
Type
1
Default
1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing
2. While the zeroing operation is in progress, the CPU is locked out from accessing the statistics RAM until
the
“
zero counter
”
bit has been reset back to
‘
0
’
. This time period is roughly 15
μ
s.
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