參數(shù)資料
型號: 97042-11
廠商: PEREGRINE SEMICONDUCTOR CORP
元件分類: PLL合成/DDS/VCOs
英文描述: PHASE LOCKED LOOP, 300 MHz, CQCC44
封裝: CERAMIC, QFJ-44
文件頁數(shù): 6/11頁
文件大?。?/td> 456K
代理商: 97042-11
Product Specification
PE97042
Page 4 of 11
2007-2011 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0236-05
│ UltraCMOS RFIC Solutions
Note: 1. Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Table 4. ESD Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
Table 5. DC Characteristics: VDD = 3.3 V, -40 °C < TA < 85 °C, unless otherwise specified
Symbol
Parameter/Conditions
Level
Units
VESD
ESD voltage (Human Body Mod-
el) – Note 1
1000
V
Table 2. Absolute Maximum Ratings
Table 3. Operating Ratings
Symbol
Parameter/Conditions
Min
Max
Units
VDD
Supply voltage
-0.3
4.0
V
VI
Voltage on any input
-0.3
VDD
+ 0.3
V
II
DC into any input
-10
+10
mA
IO
DC into any output
-10
+10
mA
Tstg
Storage temperature
range
-65
150
°C
Symbol
Parameter/Conditions
Min
Max
Units
VDD
Supply voltage
2.85
3.45
V
TA
Operating ambient
temperature range
-40
85
C
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IDD
Operational supply current;
VDD = 3.30 V
Prescaler disabled
15
mA
Prescaler enabled
45
50
mA
Digital Inputs: All except FR, FIN (all digital inputs have 70 k pull-up resistors)
VIH
High level input voltage
VDD = 2.85-3.45 V
0.7 x VDD
V
VIL
Low level input voltage
VDD = 2.85-3.45 V
0.3 x VDD
V
IIH
High level input current
VIH = VDD = 3.45 V
1
μA
IIL
Low level input current
VIL = 0, VDD = 3.45 V
-70
μA
Reference Divider input: FR
IIHR
High level input current
VIH = VDD = 3.45 V
100
μA
IILR
Low level input current
VIL = 0, VDD = 3.45 V
-100
μA
Counter and phase detector outputs: fc, fp.
VOLD
Output voltage LOW
Iout = 6 mA
0.4
V
VOHD
Output voltage HIGH
Iout = -3 mA
VDD - 0.4
V
Lock detect outputs: CEXT, LD
VOLC
Output voltage LOW, CEXT
Iout = 100 A
0.4
V
VOHC
Output voltage HIGH, CEXT
Iout = -100 A
VDD - 0.4
V
VOLLD
Output voltage LOW, LD
Iout = 1 mA
0.4
V
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