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參數(shù)資料
| 型號： | 97042-11 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 300 MHz, CQCC44 |
| 封裝： | CERAMIC, QFJ-44 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 456K |
| 代理商： | 97042-11 |
Product Specification
PE97042
Page 3 of 11
Document No. 70-0236-05
│ www.psemi.com
2007-2011 Peregrine Semiconductor Corp. All rights reserved.
Table 1. Pin Descriptions (continued)
Notes 1. VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
2. All digital input pins have 70 k
pull-up resistors to V
DD.
Pin No.
Pin Name
Interface Mode
Type
Description
17
GND
Both
Ground
18
CLOCK
Serial
Input
Clock input. Data is clocked serially into either the 20-bit primary register (E_WR
“l(fā)ow”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of
CLOCK.
M6
Direct
Input
M Counter bit6
19
M7
Direct
Input
M Counter bit7
20
M8
Direct
Input
M Counter bit8 (MSB)
21
A0
Direct
Input
A Counter bit0
22
DMODE
Both
Input
Selects direct interface mode (DMODE = 1) or serial interface mode (DMODE = 0)
23
VDD
Both
(Note 1)
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
24
E_WR
Serial
Input
Enhancement register write enable. While E_WR is “high”, DATA can be serially
clocked into the enhancement register on the rising edge of CLOCK.
A1
Direct
Input
A Counter bit1.
25
A2
Direct
Input
A Counter bit2
26
A3
Direct
Input
A Counter bit3 (MSB)
27
FIN
Both
Input
Prescaler input from the VCO, 3.5 GHz max frequency. A 22 pF coupling capacitor
should be placed as close as possible to this pin and terminated with a 50
Ω
resistor to ground.
28
Both
Input
Prescaler complementary input. A 22 pF bypass capacitor should be placed as
close as possible to this pin and be connected in series with a 50
Ω resistor to
ground.
29
GND
Both
Ground.
30
N/C
No connect.
31
VDD
Both
(Note 1)
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
32
DOUT
Serial
Output
Data Out. The Main Counter output, R Counter output, or dual modulus prescaler
select (MSEL) can be routed to DOUT through enhancement register programming.
33
VDD
Both
(Note 1)
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
34
N/C
No connect.
35
GND
Both
Ground.
36
PD_
D
Both
Output
PD_
D pulses down when fp leads fc.
37
PD_
U
Both
PD_
U pulses down when fc leads fp.
38
VDD
Both
(Note 1)
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
39
CEXT
Both
Output
Logical “NAND” of PD_
U and PD_D, passed through an on-chip, 2 k series
resistor. Connecting CEXT to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
40
GND
Both
Ground
41
GND
Both
Ground
42
FR
Both
Input
Reference frequency input
43
ENH
Both
Output
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
44
LD
Serial
Output
Lock detect output, the open-drain logical inversion of CEXT. When the loop is
locked, LD is high impedance; otherwise LD is a logic low (“0”).
FIN
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