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參數(shù)資料
| 型號(hào)： | 95V842AFILF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, LEAD FREE, MO-137, SSOP-16 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 75K |
| 代理商： | 95V842AFILF-T |
2
ICS95V842
0830B—11/24/08
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
VDD2.5
PWR
Power supply, nominal 2.5V
2
DDRT0
OUT
"True" Clock of differential pair output.
3
DDRC0
OUT
"Complementary" Clock of differential pair output.
4
GND
PWR
Ground pin.
5
CLK_INT
IN
"True" reference clock input.
6
CLK_INC
IN
"Complementary" reference clock input.
7
AVDD
PWR
3.3V Analog Power pin for Core PLL
8
AGND
PWR
Analog Ground pin for Core PLL
9
FB_OUTC
OUT
Complement single-ended feedback output, dedicated external
feedback. It switches at the same frequency as other DDR outputs,
This output must be connect to FB_INC.
10
FB_OUTT
OUT
True single-ended feedback output, dedicated external feedback. It
switches at the same frequency as other DDR outputs, This output
must be connect to FB_INT.
11
FB_INT
IN
True single-ended feedback input, provides feedback signal to internal
PLL for synchronization with CLK_INT to eliminate phase error.
12
FB_INC
IN
Complement single-ended feedback input, provides feedback signal to
internal PLL for synchronization with CLK_INT to eliminate phase
error.
13
VDD2.5
PWR
Power supply, nominal 2.5V
14
DDRT1
OUT
"True" Clock of differential pair output.
15
DDRC1
OUT
"Complementary" Clock of differential pair output.
16
GND
PWR
Ground pin.
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| 95V842YFLF-T | 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 95V842YFILF | 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 95V842AFLF | 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 95V842AFLF-T | 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 95V842AF-T | 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 95V842AFLF | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 95V842AFLFT | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 95V847AG | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 1:5, 2.5V Phase-Lock Loop Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 95V847AGI | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Driver Single 45MHz to 233MHz 24-Pin TSSOP Tube 制造商:Integrated Device Technology Inc 功能描述:1:5, 2.5V Phase-Lock Loop Clock Driver |
| 95V847AGIT | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Driver Single 45MHz to 233MHz 24-Pin TSSOP T/R 制造商:Integrated Device Technology Inc 功能描述:1:5, 2.5V Phase-Lock Loop Clock Driver |
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