參數(shù)資料
型號(hào): 95V842AFLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 0.150 INCH, LEAD FREE, MO-137, SSOP-16
文件頁數(shù): 1/9頁
文件大?。?/td> 75K
代理商: 95V842AFLF
1
ICS95V842
0830B—11/24/08
Block Diagram
DDR Phase Lock Loop Clock Driver (60MHz - 220MHz)
Pin Configuration
Recommended Application:
1:2 DDRI Clock Driver
Product Description/Features:
Low skew, low jitter PLL clock driver
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
With bypass mode mux
Operating frequency 60 to 220 MHz
Switching Characteristics:
CYCLE - CYCLE jitter: <75ps
OUTPUT - OUTPUT skew: <60ps
Period jitter: ±75ps
Half-Period jitter: ±75ps
Functionality
S
T
U
P
N
IS
T
U
P
T
U
O
e
t
a
t
S
L
P
D
V
AT
N
I
_
K
L
CC
N
I
_
K
L
CT
K
L
CC
K
L
CT
T
U
O
_
B
FC
T
U
O
_
B
F
D
N
GL
H
L
H
L
H
f
O
/
d
e
s
a
p
y
B
D
N
GH
L
H
L
H
L
f
O
/
d
e
s
a
p
y
B
V
5
.
2
)
m
o
n
(
LH
L
H
L
H
n
O
V
5
.
2
)
m
o
n
(
HL
H
L
H
L
n
O
VDD2.5 1
16 GND
DDRT0 2
15 DDRC1
DDRC0 3
14 DDRT1
GND 4
13 VDD2.5
CLK_INT 5
12 FB_INC
CLK_INC 6
11 FB_INT
AVDD 7
10 FB_OUTT
AGND 8
9 FB_OUTC
16 pin SSOP
IC
S
95V
842
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
FB_OUTT
FB_OUTC
DDRT (1:0)
DDRC(1:0)
AVDD
相關(guān)PDF資料
PDF描述
95V842AFLF-T 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
95V842AF-T 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
95V842AF 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
95V842YFILF-T 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
95V842YF-T 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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