參數(shù)資料
型號(hào)： 952601YGLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56
文件頁(yè)數(shù)： 6/25頁(yè)
文件大?。?/td> 227K
代理商： 952601YGLFT
IDTTM
Progammable Timing Control HubTM for Next Gen P4TM Processor
701J—01/25/10
ICS952601
Programmable Timing Control HubTM for Next Gen P4TM Processor
14
The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to
be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the
PCI_STOP register bit.
PCI Stop Functionality
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The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all
PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low,
the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and
the SRC# will latch low as shown below.
PCI_STOP#
Tsu
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# Assertion (transition from '1' to '0')
The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After
detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free
manner.
PCI_STOP#
Tsu
Tdrive_SRC
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# - De-assertion
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