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參數(shù)資料
| 型號： | 952601YFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.25 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 227K |
| 代理商： | 952601YFLFT |
IDTTM
Progammable Timing Control HubTM for Next Gen P4TM Processor
701J—01/25/10
ICS952601
Programmable Timing Control HubTM for Next Gen P4TM Processor
5
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Notes
VDD_A
3.3V Core Supply Voltage
VDD + 0.5V
V
VDD_In
3.3V Logic Input Supply Voltage
GND - 0.5
VDD + 0.5V
V
Ts
Storage Temperature
-65
150
°C
Tambient
Ambient Operating Temp
0
70
°C
Tcase1
Case Temperature 1
115
°C
1
Tcase2
Case Temperature 2
94
°C
2
ESD prot
Input ESD protection human body model
2000
V
1. This case temperature limits the junction temperature to <150 °C for package reliabilty
2. This case temperature limits the junction temperature to <125 °C for long term silicon reliability
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
Input MID Voltage
VMID
3.3 V +/-5%
1
1.8
V
Input Low Voltage
VIL
3.3 V +/-5%
VSS - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
uA
IIL1
VIN = 0 V; Inputs with no pull-
up resistors
-5
uA
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
Operating Supply Current
IDD3.3OP
Full Active, CL = Full load;
258
350
mA
all diff pairs driven
29
35
mA
all differential pairs tri-stated
0.3
12
mA
Input Frequency
3
Fi
VDD = 3.3 V
14.31818
MHz
3
Pin Inductance
1
Lpin
7nH
1
CIN
Logic Inputs
5
pF
1
COUT
Output pin capacitance
6
pF
1
CINX
X1 & X2 pins
5
pF
1
Clk Stabilization
1,2
TSTAB
From VDD Power-Up or de-
assertion of PD# to 1st clock
1.8
ms
1,2
Modulation Frequency
Triangular Modulation
30
33
kHz
1
Tdrive_SRC
SRC output enable after
PCI_Stop# de-assertion
15
ns
1
Tdrive_PD#
CPU output enable after
PD# de-assertion
300
us
1
Tfall_Pd#
PD# fall time of
5
ns
1
Trise_Pd#
PD# rise time of
5
ns
2
Tdrive_CPU_Stop#
CPU output enable after
CPU_Stop# de-assertion
10
us
1
Tfall_CPU_Stop#
PD# fall time of
5
ns
1
Trise_CPU_Stop#
PD# rise time of
5
ns
2
SMBus Voltage
VDD
2.7
5.5
V
1
Low-level Output Voltage
VOL
@ IPULLUP
0.4
V
1
Current sinking at VOL = 0.4 V
IPULLUP
4mA
1
SCLK/SDATA
Clock/Data Rise Time
3
TRI2C
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
3
TFI2C
(Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
1
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
IDD3.3PD
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency
accuracy on PLL outputs.
Input Capacitance
1
Input Low Current
Powerdown Current
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 952601YGLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Programmable Timing Control HubTM for Next Gen P4TM Processor |
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