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參數(shù)資料
| 型號： | 952302AGT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 153K |
| 代理商： | 952302AGT |
14
ICS952302
0957B—10/05/04
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS952302. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS952302 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is
one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS952302 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS952302.
3. All other clocks continue to run undisturbed.
4. CLK_STOP# is shown in a high (true) state.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CLK_STOP#
PCICLK
PCI_STOP#
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