參數(shù)資料
型號(hào)： 952302AGT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
文件頁(yè)數(shù)： 12/17頁(yè)
文件大小： 153K
代理商： 952302AGT
4
ICS952302
0957B—10/05/04
Control
Function
Bit 7
CPUCLK_F
Output Enable
RW
Disable
Enable
1
Bit 6
CPUCLK0
Output Enable
RW
Disable
Enable
1
Bit 5
CPUCLK1
Output Enable
RW
Disable
Enable
1
Bit 4
27MHZ
Output Enable
RW
Disable
Enable
1
Bit 3
48MHZ_0
Output Enable
RW
Disable
Enable
1
Bit 2
48MHZ_1
Output Enable
RW
Disable
Enable
1
Bit 1
REF0
Output Enable
RW
Disable
Enable
1
Bit 0
REF1
Output Enable
RW
Disable
Enable
1
Control
Function
Bit 7
PCICLK_F0
Test Mode
RW
Disable
Enable
1
Bit 6
PCICLK_F1
Output Enable
RW
Disable
Enable
1
Bit 5
PCICLK_F2
Output Enable
RW
Disable
Enable
1
Bit 4
PCICLK_F3
Output Enable
RW
Disable
Enable
1
Bit 3
PCICLK0
Spread Control
RW
Disable
Enable
1
Bit 2
PCICLK1
Output Enable
RW
Disable
Enable
1
Bit 1
PCICLK2
Output Enable
RW
Disable
Enable
1
Bit 0
Spread Spectrum
Mode
Spread Control for PLL1
RW
OFF
ON
0
Control
Function
Bit 7
CPUCLK_F
RW
Free Running
Stoppable
0
Bit 6
CPUCLK0
RW
Free Running
Stoppable
1
Bit 5
CPUCLK1
RW
Free Running
Stoppable
1
Bit 4
Reserved
RW
-
x
Bit 3
Reserved
RW
-
x
Bit 2
CPU_STOP
Stop all CPU clocks
RW
Enable
Disable
1
Bit 1
Reserved
RW
-
x
Bit 0
CPU_STOP#
PCI_STOP#
H/w or S/w Select
RW
H/W
I2C
1
Control
Function
Bit 7
PCICLK_F0
RW
Free Running
Stoppable
0
Bit 6
PCICLK_F1
RW
Free Running
Stoppable
0
Bit 5
PCICLK_F2
RW
Free Running
Stoppable
0
Bit 4
PCICLK_F3
RW
Free Running
Stoppable
0
Bit 3
PCICLK0
RW
Free Running
Stoppable
1
Bit 2
PCICLK1
RW
Free Running
Stoppable
1
Bit 1
PCICLK2
RW
Free Running
Stoppable
1
Bit 0
PCI_STOP
Stop all PCI clocks
RW
Enable
Disable
1
7
8
11
12
15
-
13
10
PWD
01
Byte 1
Pin #
Name
Type
2
48
43
32
25
26
PWD
45
Byte 0
Pin #
Name
Type
42
01
Note: Byte2bit2=0 (Enable) to stop all CPUCLK's ONLY when Byte2 bit(5:7) at STOPPABLE MODE
Pin #
Name
Type
11
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop PCI
clocks
45
Allow assertion of
CPU_STOP# or setting of
CPU_STOP control bit in
SMBus register to stop
CPU clocks
20, 41
7
15
-
13
43
(note)
-
12
8
Byte 3
10
SMBus Table: Output Control Register
1
0PWD
SMBus Table: Output Control Register
0
Byte 2
Pin #
Name
Type
PWD
1
42
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