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參數(shù)資料
| 型號： | 952302AGT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 153K |
| 代理商： | 952302AGT |
2
ICS952302
0957B—10/05/04
Pin Descriptions
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
1
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
2
REF0
OUT
14.318 MHz reference clock.
3
GNDREF
PWR
Ground pin for the REF outputs.
4X1
IN
Crystal input, Nominally 14.318MHz.
5
X2
OUT
Crystal output, Nominally 14.318MHz
6
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
7
PCICLK_F0
OUT
Free running PCI clock not affected by PCI_STOP# .
8
PCICLK_F1
OUT
Free running PCI clock not affected by PCI_STOP# .
9
GNDPCI
PWR
Ground pin for the PCI outputs
10
PCICLK0
OUT
PCI clock output.
11
PCICLK1
OUT
PCI clock output.
12
PCICLK_F2
OUT
Free running PCI clock not affected by PCI_STOP# .
13
PCICLK_F3
OUT
Free running PCI clock not affected by PCI_STOP# .
14
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
15
PCICLK2
OUT
PCI clock output.
16
GNDPCI
PWR
Ground pin for the PCI outputs
17
N/C
No Connection.
18
N/C
No Connection.
19
VDDCOR
PWR
3.3V power for the PLL core.
20
PCI_STOP#
IN
Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input.
21
**PD#
IN
Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used to power down the device. The
internal clocks are disabled and the VCO and the crystal are stopped.
22
GND48
PWR
Ground pin for the 48MHz outputs
23
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
24
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
25
48MHZ_0
OUT
48MHz clock output.
26
48MHZ_1
OUT
48MHz clock output.
27
VDD48
PWR
Power pin for the 48MHz output.3.3V
28
GND48
PWR
Ground pin for the 48MHz outputs
29
N/C
No Connection.
30
N/C
No Connection.
31
N/C
No Connection.
32
27MHZ
OUT
27.0000MHz Video Clock for ATi Chipset
33
GND
PWR
Ground pin.
34
VDD27
PWR
Power pin for the 27MHz output.3.3V
35
N/C
No Connection.
36
VDD
PWR
Power supply, nominal 3.3V
37
N/C
No Connection.
38
OE*
IN
Active high input for enabling Memory Channel outputs.
0 = tri-state outputs, 1= enable outputs
39
N/C
No Connection.
40
GND
PWR
Ground pin.
41
CPU_STOP#
IN
Stops all CPUCLK, except those set to be free running clocks
42
CPUCLK_F
OUT
Free running CPU clock. Not affected by the CPU_STOP#.
43
CPUCLK1
OUT
CPU clock outputs. 3.3V
44
GNDCPU
PWR
Ground pin for the CPU outputs
45
CPUCLK0
OUT
CPU clock outputs. 3.3V
46
N/C
No Connection.
47
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
48
REF1
OUT
14.318 MHz reference clock.
* Internal Pull-Up Resistor
** No diode clamp to VDD.
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