參數資料
型號: 951413CFLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 0.300 INCH, 0.025 INCH PITCH, GREEN, MO-118, SSOP-56
文件頁數: 3/26頁
文件大?。?/td> 257K
代理商: 951413CFLFT
11
Integrated
Circuit
Systems, Inc.
ICS951413
0929D—10/30/06
SMBus Table: Device ID Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
DevID 7
Device ID MSB
R
-
0
Bit 6
DevID 6
Device ID 6
R
-
0
Bit 5
DevID 5
Device ID 5
R
-
0
Bit 4
DevID 4
Device ID4
R
-
1
Bit 3
DevID 3
Device ID3
R
-
0
Bit 2
DevID 2
Device ID2
R
-
0
Bit 1
DevID 1
Device ID1
R
-
1
Bit 0
DevID 0
Device ID LSB
R
-
1
SMBus Table: Vendor ID Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
RID3
R
-
X
Bit 6
RID2
R
-
X
Bit 5
RID1
R
-
X
Bit 4
RID0
R
-
X
Bit 3
VID3
R
-
0
Bit 2
VID2
R
-
0
Bit 1
VID1
R
-
0
Bit 0
VID0
R
-
1
SMBus Table: Byte Count Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
BC7
RW
0
Bit 6
BC6
RW
0
Bit 5
BC5
RW
0
Bit 4
BC4
RW
0
Bit 3
BC3
RW
1
Bit 2
BC2
RW
0
Bit 1
BC1
RW
0
Bit 0
BC0
RW
1
SMBus Table: WD TimeR Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
WDH_EN
Watchdog Hard Alarm
Enable
RW
Disable
Enable
0
Bit 6
WDS_EN
Watchdog Soft Alarm
Enable
RW
Disable
Enable
0
Bit 5
WD Hard Status
WD Hard Alarm Status
R
Normal
Alarm
X
Bit 4
WD Soft Status
WD Soft Alarm Status
R
Normal
Alarm
X
Bit 3
WDTCtrl
Watch Dog Time base
Control
RW 290ms Base
1160ms
Base
0
Bit 2
WD2
WD Timer Bit 2
RW
1
Bit 1
WD1
WD Timer Bit 1
RW
1
Bit 0
WD0
WD Timer Bit 0
RW
1
-
Byte 9
-
Byte 8
-
Byte Count
Programming b(7:0)
Writing to this register
will configure how many
bytes will be read back,
default is 9 bytes.
-
VENDOR ID
(0001 = ICS)
-
Byte 7
-
Revision ID
Starts at 0 hex for A
revsion.
-
Byte 6
-
These bits represent
X*290ms (or 1.16S) the
watchdog timer waits
before it goes to alarm
mode. Default is 7 X
290ms = 2s.
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951413CFLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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