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參數(shù)資料
| 型號： | 94201DF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, SSOP-56 |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 222K |
| 代理商： | 94201DF |
6
ICS94201
0428B - 11/28/05
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Byte 5: Output Control Register
(1 = enable, 0 = disable)
Byte 6: Byte Count Read Back Register
Note: Writing to this register will configure byte count and
how many bytes will be read back, default is 6 bytes.
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